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1. A time-sharing system implies:
More than one processor in the memory
More than one program in the memory
More than one memory in the system
None of above
2. A multiprocessor computer is of the type:
SISD
MIMD
SIMD
All of the above
3. Microprocessor is a device which has at least:
Memory
Registers
I/O devices
CPU
4. A supercomputer has the capabilities of execution:
Pipeline instruction
Floating point arithmetic operation
Vector instruction
All of the above
5. The maximum stages in pipelining architecture are:
4
6
2
5
6. Instruction pipelining has minimum stages:
4
6
2
3
7. Systems do not have parallel processing capabilities are:
SISD
MIMD
SIMD
All of the above
8. Memory access in RISC architecture is limited to instructions:
CALL & RET
STA & LDA
PUSH & POP
MOV & JMP
9. Interrupt which are initiated by an I/O device are:
Internal
Software
External
All of the above
10. Interrupt which are initiated by an instruction are:
Hardware
Internal
External
Software
11. States bit of the CPU are stored in a flag:
Carry
Zero
Sign
All of the above
12. The effective address is the address of the operand in an instruction of type:
Immediate
Register
Indirect
Computational
13. Program counter of a CPU stores the address of the instruction:
Currently executed
Just executed
To be executed next
None of the above
14. A stack-organized computer has:
Three-address instruction
One-address instruction
Two-address instruction
Zero-address instruction
15. The operation performed on stack are:
IN & OUT
PUSH & POP
CALL & RET
POP & OUT
16. The stack is the list of type:
LIFO
FILO
LILO
All of the above
17. A microprocessor consists of:
Control unit
ALU
Program counter
All of the above
18. A microprocessor sequencer performs the operation:
Read
Execute
Write
Read and execute
19. A microprogram written as a string of 0's and 1's is a:
Symbolic microinstruction
Binary microprogram
Binary microinstruction
All of the above
20. The branch logic that provides decision-making capabilities in the control unit is known as:
Controlled transfer
Unconditional transfer
Conditional transfer
None of the above
21. A control unit whose binary control variables are stored in memory is known as:
Hardwired control unit
Software control unit
Micro-programmed control unit
Hardware control unit
22. During execution, subroutine return address is stored in:
Control address register
Stack pointer
Subroutine address
Memory location
23. The next address generator is sometimes called a:
Instruction sequence
Micro program sequence
Program sequence
Translator
24. The control data register holds the present microinstruction and is sometimes called:
Instruction register
Sequence register
Microinstruction register
Pipeline register
25. A memory that is a part of a control unit is referred to as:
External memory
Cache memory
Internal memory
Control memory
26. Whenever POP H instruction is executed:
Data byte in the HL pair are stored on the stack
Two data bytes at the top of the stack are transferred to the HP register pair
Two data bytes at the top of the stack are transferred to the program counter
Two data bytes from the HL register that were previously stored on the stack are transferred back to the HL pointer
27. When the RET instruction at the end of a subroutine is executed:
The information where the stack is initialized is transferred to the stack pointer
The memory address of the RET instructions is transferred to the program counter
Two data bytes stored in the top two locations of the stack are transferred to the program counter
Two data bytes stored in the top two locations of the stack are transferred to the stack pointer
28. When a subroutine is called, the address of the instruction following the CALL is stored in/on the:
Stack pointer
Program counter
Accumulator
Stack
29. A stack pointer is:
A 16-bit register in the microprocessor that indicates the beginning of the stack memory
A register that decodes and executes 16-bit arithmetic expressions
The first memory locations where a subroutine address is stored
A register in which flag bits are stored
30. A stack is:
An 8-bit register in the microprocessor
A set of memory locations in R/WM reserved for storing information temporarily during the execution of a program
A 16-bit memory address stored in the program counter
A 16-bit register in the microprocessor
31. A third and last component of CPU is:
ALU
Supervisor – control unit
Input device
Register unit
32. The section of the CPU that selects, interprets, and sees to the execution of program instructions is:
Memory
Control unit
Register unit
ALU
33. A device used to bring information into a computer is:
ALU
Control unit
Input device
Output device
34. A microprocessor is a..... on a chip:
Computer
ALU
CPU
Control unit
35. Part of the computer where the data and instructions are held is:
Register unit
Memory unit
Accumulator
CPU
36. Backing storage is so named because:
It is always kept at the back of the CPU
It backs up the computer's main memory
It lags behind the main memory
It is slow and backward
37. The ALU and control unit of most of the microcomputers are combined and manufactured on a single silicon chip. What is it called?
Monochip
ALU
Microprocessor
Control unit
38. Which of the following code used in present-day computing was developed by IBM corporation?
ASCII
Baudot code
Hollerith code
EBCDIC CODE
39. Which parts of the computer are used for calculating and comparing?
Disk unit
ALU
Control unit
Modem
40. Instruction LXI in 8085 loads:
Stack pointer
None of the above
Register pair
All of the above
41. A CALL instruction is always encountered by instructions:
IN
OUT
RET
INTR
42. In I/O mapped I/O 8085 duplicates the I/O address on:
Address and data line
Lower byte of address and control line
Lower and higher byte of address
Higher byte of address and data line
43. Address and data line in 8085 are:
Separate lines
Only lower byte of address is multiplexed
Common line
Shared line
44. The 16-bit register in 8085 is:
General purpose register
Stack pointer and program counter
Accumulator
All of the above
45. Microprocessor 8085 can address location up to:
32K
64K
128K
1M
46. Pipeline processing implements:
Fetch instructions
Fetch operand
Decode instruction
All of the above
47. Pipeline strategy is called implement:
Instruction execution
Instruction decoding
Instruction pre-fetch
Instruction manipulation
48. Intel 80486 pipelining implements stages:
6
5
4
3
49. Pipeline processing uses the technique:
Sharing the memory
Pre-fetching
Bit slicing
Parallel processing
50. Micro instructions are stored in:
Computer memory
Secondary storage
Primary memory
Control memory
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