set-7

301. The output of an SR flip-flop when S=1S = 1 and R=0R = 0 is:

  1. 11

  2. No change\text{No change}

  3. 00

  4. High impedance\text{High impedance}

Show me the answer

Answer: 1. 11

Explanation:

  • When S=1S = 1 and R=0R = 0, the SR flip-flop sets the output to 11.

302. The number of flip-flops contained in IC 7490 is:

  1. 22

  2. 44

  3. 33

  4. 1010

Show me the answer

Answer: 2. 44

Explanation:

  • The IC 7490 contains 4 flip-flops.

303. The number of control lines for a 32-to-1 multiplexer is:

  1. 44

  2. 1616

  3. 55

  4. 66

Show me the answer

Answer: 3. 55

Explanation:

  • A 32-to-1 multiplexer requires 55 control lines because 25=322^5 = 32.

304. How many two-input AND & OR gates are required to realize Y=CD+EF+GY = CD + EF + G?

  1. 2,22, 2

  2. 3,33, 3

  3. 2,32, 3

  4. None of these\text{None of these}

Show me the answer

Answer: 1. 2,22, 2

Explanation:

  • Two AND gates are required for CDCD and EFEF, and two OR gates are required for combining the terms.

305. Which of the following cannot be accessed randomly?

  1. DRAM\text{DRAM}

  2. ROM\text{ROM}

  3. SRAM\text{SRAM}

  4. Magnetic tape\text{Magnetic tape}

Show me the answer

Answer: 4. Magnetic tape\text{Magnetic tape}

Explanation:

  • Magnetic tape is a sequential access memory and cannot be accessed randomly.

306. The excess-3 code of decimal 7 is represented by:

  1. 11001100

  2. 10111011

  3. 10011001

  4. 10101010

Show me the answer

Answer: 2. 10111011

Explanation:

  • The excess-3 code of 7 is obtained by adding 3 to 7, resulting in 1010, which is 10101010 in binary.

307. When an input signal A=11001A = 11001 is applied to a NOT gate serially, its output signal is:

  1. 0011100111

  2. 1010110101

  3. 0011000110

  4. 1100111001

Show me the answer

Answer: 3. 0011000110

Explanation:

  • The NOT gate inverts each bit of the input signal, so 1100111001 becomes 0011000110.

308. The result of adding the hexadecimal number A6 to 3A is:

  1. DDDD

  2. F0F0

  3. E0E0

  4. EFEF

Show me the answer

Answer: 3. E0E0

Explanation:

  • Adding A6 (166166 in decimal) and 3A (5858 in decimal) gives E0 (224224 in decimal).

309. A universal logic gate is one that can be used to generate any logic function. Which of the following is a universal logic gate?

  1. OR\text{OR}

  2. XOR\text{XOR}

  3. AND\text{AND}

  4. NAND\text{NAND}

Show me the answer

Answer: 4. NAND\text{NAND}

Explanation:

  • NAND gates are universal because they can be used to implement any logic function.

310. The logic 0 level of a CMOS logic device is approximately:

  1. 1.2 volts1.2 \text{ volts}

  2. 5 volts5 \text{ volts}

  3. 0.4 volts0.4 \text{ volts}

  4. 0 volts0 \text{ volts}

Show me the answer

Answer: 4. 0 volts0 \text{ volts}

Explanation:

  • In CMOS logic, a logic 0 is represented by a voltage close to 00 volts.

311. A Karnaugh map is used for the purpose of:

  1. Reducing the electronic circuits used\text{Reducing the electronic circuits used}

  2. Mapping the given Boolean logic function\text{Mapping the given Boolean logic function}

  3. Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}

  4. Maximizing the terms of a given Boolean expression\text{Maximizing the terms of a given Boolean expression}

Show me the answer

Answer: 3. Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}

Explanation:

  • Karnaugh maps are used to simplify Boolean expressions by minimizing the number of terms.

312. A full adder logic circuit will have:

  1. Two inputs and one output\text{Two inputs and one output}

  2. Three inputs and three outputs\text{Three inputs and three outputs}

  3. Two inputs and two outputs\text{Two inputs and two outputs}

  4. Three inputs and two outputs\text{Three inputs and two outputs}

Show me the answer

Answer: 4. Three inputs and two outputs\text{Three inputs and two outputs}

Explanation:

  • A full adder has three inputs (A, B, and carry-in) and two outputs (sum and carry-out).

313. An eight-stage ripple counter uses flip-flops with a propagation delay of 75 nanoseconds each. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately:

  1. 1 MHz1 \text{ MHz}

  2. 2 MHz2 \text{ MHz}

  3. 500 MHz500 \text{ MHz}

  4. 4 MHz4 \text{ MHz}

Show me the answer

Answer: 1. 1 MHz1 \text{ MHz}

Explanation:

  • The maximum frequency is determined by the total propagation delay, which is 8×75 ns=600 ns8 \times 75 \text{ ns} = 600 \text{ ns}. The frequency is 1/600 ns≈1.67 MHz1 / 600 \text{ ns} \approx 1.67 \text{ MHz}, so 1 MHz is the closest option.

314. The output of a JK flip-flop with asynchronous preset and clear inputs is '1'. The output can be changed to '0' with one of the following conditions:

  1. By applying J=0,K=0 and using a clock\text{By applying } J = 0, K = 0 \text{ and using a clock}

  2. By applying J=1,K=0 and using the clock\text{By applying } J = 1, K = 0 \text{ and using the clock}

  3. By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}

  4. By applying a synchronous preset input\text{By applying a synchronous preset input}

Show me the answer

Answer: 3. By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}

Explanation:

  • When J=1J = 1 and K=1K = 1, the JK flip-flop toggles its output on the clock pulse, changing it from 1 to 0.

315. The information in ROM is stored:

  1. By the user any number of times\text{By the user any number of times}

  2. By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}

  3. By the user using ultraviolet light\text{By the user using ultraviolet light}

  4. By the user once and only once\text{By the user once and only once}

Show me the answer

Answer: 2. By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}

Explanation:

  • ROM (Read-Only Memory) is programmed by the manufacturer and cannot be modified by the user.

316. The conversion speed of an analog-to-digital converter is maximum with the following technique:

  1. Dual slope A/D converter\text{Dual slope A/D converter}

  2. Serial comparator A/D converter\text{Serial comparator A/D converter}

  3. Successive approximation A/D converter\text{Successive approximation A/D converter}

  4. Parallel comparator A/D converter\text{Parallel comparator A/D converter}

Show me the answer

Answer: 4. Parallel comparator A/D converter\text{Parallel comparator A/D converter}

Explanation:

  • Parallel comparator A/D converters have the fastest conversion speed.

317. A weighted resistor digital-to-analog converter using N bits requires a total of:

  1. N precision resistorsN \text{ precision resistors}

  2. N+1 precision resistorsN + 1 \text{ precision resistors}

  3. 2N precision resistors2N \text{ precision resistors}

  4. N−1 precision resistorsN - 1 \text{ precision resistors}

Show me the answer

Answer: 1. N precision resistorsN \text{ precision resistors}

Explanation:

  • A weighted resistor DAC requires one precision resistor for each bit.

318. The 2's complement of the number 1101110 is:

  1. 00100010010001

  2. 00100100010010

  3. 00100010010001

  4. None\text{None}

Show me the answer

Answer: 2. 00100100010010

Explanation:

  • The 2's complement of 1101110 is obtained by inverting the bits and adding 1, resulting in 00100100010010.

319. The decimal equivalent of the binary number 10101 is:

  1. 2121

  2. 2626

  3. 3131

  4. 2828

Show me the answer

Answer: 1. 2121

Explanation:

  • The binary number 1010110101 converts to the decimal number 2121.

320. How many two-input AND gates and two-input OR gates are required to realize Y=BD+CE+ABY = BD + CE + AB?

  1. 1,11, 1

  2. 3,23, 2

  3. 4,24, 2

  4. 2,32, 3

Show me the answer

Answer: 2. 3,23, 2

Explanation:

  • Three AND gates are required for BDBD, CECE, and ABAB, and two OR gates are required for combining the terms.

321. How many select lines will a 32-to-1 multiplexer have?

  1. 55

  2. 99

  3. 88

  4. 1111

Show me the answer

Answer: 1. 55

Explanation:

  • A 32-to-1 multiplexer requires 55 select lines because 25=322^5 = 32.

322. How many address bits are required to represent 4K memory?

  1. 5 bits5 \text{ bits}

  2. 8 bits8 \text{ bits}

  3. 12 bits12 \text{ bits}

  4. 10 bits10 \text{ bits}

Show me the answer

Answer: 3. 12 bits12 \text{ bits}

Explanation:

  • A 4K memory requires log⁡2(4096)=12\log_2(4096) = 12 address bits.

323. For a JK flip-flop with J=0J = 0 and K=1K = 1, the output after a clock pulse will be:

  1. 11

  2. 00

  3. No change\text{No change}

  4. High impedance\text{High impedance}

Show me the answer

Answer: 2. 00

Explanation:

  • When J=0J = 0 and K=1K = 1, the JK flip-flop resets the output to 00.

324. Which of the following are known as universal gates?

  1. NAND and NOR\text{NAND and NOR}

  2. XOR and OR\text{XOR and OR}

  3. AND and OR\text{AND and OR}

  4. None\text{None}

Show me the answer

Answer: 1. NAND and NOR\text{NAND and NOR}

Explanation:

  • NAND and NOR gates are universal because they can be used to implement any logic function.

325. Which of the following memories stores the most number of bits?

  1. 64Kx8 memory\text{64Kx8 memory}

  2. 32Mx8 memory\text{32Mx8 memory}

  3. 1Mx8 memory\text{1Mx8 memory}

  4. 64x6 memory\text{64x6 memory}

Show me the answer

Answer: 2. 32Mx8 memory\text{32Mx8 memory}

Explanation:

  • A 32Mx8 memory stores 32×8=25632 \times 8 = 256 million bits, which is the largest among the options.

326. Which of the following consumes minimum power?

  1. TTL\text{TTL}

  2. DTL\text{DTL}

  3. CMOS\text{CMOS}

  4. RTL\text{RTL}

Show me the answer

Answer: 3. CMOS\text{CMOS}

Explanation:

  • CMOS logic consumes the least power among the given options.

327. The complement of a variable is always:

  1. 00

  2. Equal to the variable\text{Equal to the variable}

  3. 11

  4. The inverse of the variable\text{The inverse of the variable}

Show me the answer

Answer: 4. The inverse of the variable\text{The inverse of the variable}

Explanation:

  • The complement of a variable is its inverse (e.g., A‾\overline{A}).

328. The Boolean expression A+B+CA + B + C is:

  1. A sum term\text{A sum term}

  2. A product term\text{A product term}

  3. A literal term\text{A literal term}

  4. A complement term\text{A complement term}

Show me the answer

Answer: 1. A sum term\text{A sum term}

Explanation:

  • The expression A+B+CA + B + C is a sum term because it represents the logical OR of the variables.

329. The Boolean expression AB′CD′AB'CD' is:

  1. A sum term\text{A sum term}

  2. A literal\text{A literal}

  3. A product term\text{A product term}

  4. Always 1\text{Always 1}

Show me the answer

Answer: 3. A product term\text{A product term}

Explanation:

  • The expression AB′CD′AB'CD' is a product term because it represents the logical AND of the variables.

330. The domain of the expression AB′CD+AB′+C′D+BAB'CD + AB' + C'D + B is:

  1. A and DA \text{ and } D

  2. A,B,C, and DA, B, C, \text{ and } D

  3. B onlyB \text{ only}

  4. None of the above\text{None of the above}

Show me the answer

Answer: 2. A,B,C, and DA, B, C, \text{ and } D

Explanation:

  • The domain of the expression includes all variables A,B,C, and DA, B, C, \text{ and } D.

331. According to the commutative law of addition:

  1. AB=BAAB = BA

  2. A+(B+C)=(A+B)+CA + (B + C) = (A + B) + C

  3. A=A+AA = A + A

  4. A+B=B+AA + B = B + A

Show me the answer

Answer: 4. A+B=B+AA + B = B + A

Explanation:

  • The commutative law of addition states that the order of operands does not affect the result, so A+B=B+AA + B = B + A.

332. According to the associative law of multiplication:

  1. B=BBB = BB

  2. A+B=B+AA + B = B + A

  3. A(BC)=(AB)CA(BC) = (AB)C

  4. B+B(B+0)B + B(B + 0)

Show me the answer

Answer: 3. A(BC)=(AB)CA(BC) = (AB)C

Explanation:

  • The associative law of multiplication states that the grouping of operands does not affect the result, so A(BC)=(AB)CA(BC) = (AB)C.

333. According to the distributive law:

  1. A(B+C)=AB+ACA(B + C) = AB + AC

  2. A(A+1)=AA(A + 1) = A

  3. A(BC)=(AB)CA(BC) = (AB)C

  4. A+AB=AA + AB = A

Show me the answer

Answer: 1. A(B+C)=AB+ACA(B + C) = AB + AC

Explanation:

  • The distributive law states that multiplication distributes over addition, so A(B+C)=AB+ACA(B + C) = AB + AC.

334. Which one of the following is not a valid rule of Boolean algebra?

  1. A+1=1A + 1 = 1

  2. AA=AAA = A

  3. A=AA = A

  4. A+0=AA + 0 = A

Show me the answer

Answer: 3. A=AA = A

Explanation:

  • The statement A=AA = A is not a rule of Boolean algebra; it is an identity.

335. Which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?

  1. A+1=1A + 1 = 1

  2. AA=AAA = A

  3. A+A=AA + A = A

  4. A⋅1=AA \cdot 1 = A

Show me the answer

Answer: 4. A⋅1=AA \cdot 1 = A

Explanation:

  • The rule A⋅1=AA \cdot 1 = A states that if one input of an AND gate is 1, the output is equal to the other input.

336. According to De Morgan’s theorems, the following equality(s) are correct:

  1. AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}

  2. A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}

  3. XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 4. All of the above\text{All of the above}

Explanation:

  • De Morgan’s theorems state that:

    • AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}

    • A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}

    • XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}

  • All the given equalities are correct.

337. The Boolean expression X=AB+CDX = AB + CD represents:

  1. Two ORs ANDed together\text{Two ORs ANDed together}

  2. Two ANDs ORed together\text{Two ANDs ORed together}

  3. A 4-input AND gate\text{A 4-input AND gate}

  4. An exclusive-OR\text{An exclusive-OR}

Show me the answer

Answer: 2. Two ANDs ORed together\text{Two ANDs ORed together}

Explanation:

  • The expression X=AB+CDX = AB + CD represents two AND gates (ABAB and CDCD) whose outputs are ORed together.

338. An example of a sum-of-products expression is:

  1. A+B(C+D)A + B(C + D)

  2. AB+AC+ABCAB + AC + ABC

  3. (A+B+C)(A+B+C)(A + B + C)(A + B + C)

  4. Both answers A and B\text{Both answers A and B}

Show me the answer

Answer: 2. AB+AC+ABCAB + AC + ABC

Explanation:

  • A sum-of-products expression is a logical OR of multiple AND terms, such as AB+AC+ABCAB + AC + ABC.

339. An example of a sum-of-sums expression is:

  1. A(B+C)+AGA(B + C) + AG

  2. A+B+BCA + B + BC

  3. (A+B)(A+B+C)(A + B)(A + B + C)

  4. Both answers A and B\text{Both answers A and B}

Show me the answer

Answer: 3. (A+B)(A+B+C)(A + B)(A + B + C)

Explanation:

  • A sum-of-sums expression is a logical AND of multiple OR terms, such as (A+B)(A+B+C)(A + B)(A + B + C).

340. An example of a standard SOP expression is:

  1. AB+ABC+ABDAB + ABC + ABD

  2. AB+AB+ABAB + AB + AB

  3. ABC+ACDABC + ACD

  4. ABCD+AB+AABCD + AB + A

Show me the answer

Answer: 3. ABC+ACDABC + ACD

Explanation:

  • A standard SOP (Sum of Products) expression consists of AND terms combined with OR, such as ABC+ACDABC + ACD.

341. A 3-variable Karnaugh map has:

  1. Eight cells\text{Eight cells}

  2. Sixteen cells\text{Sixteen cells}

  3. Three cells\text{Three cells}

  4. Four cells\text{Four cells}

Show me the answer

Answer: 1. Eight cells\text{Eight cells}

Explanation:

  • A 3-variable Karnaugh map has 23=82^3 = 8 cells.

342. In a 4-variable Karnaugh map, a 2-variable product term is produced by:

  1. A 2-cell group of 1s\text{A 2-cell group of 1s}

  2. A 4-cell group of 1s\text{A 4-cell group of 1s}

  3. An 8-cell group of 1s\text{An 8-cell group of 1s}

  4. A 4-cell group of 0s\text{A 4-cell group of 0s}

Show me the answer

Answer: 2. A 4-cell group of 1s\text{A 4-cell group of 1s}

Explanation:

  • A 2-variable product term is produced by a 4-cell group of 1s in a 4-variable Karnaugh map.

343. On a Karnaugh map, grouping the 0s produces:

  1. A product-of-sums expression\text{A product-of-sums expression}

  2. A "don’t care" condition\text{A "don’t care" condition}

  3. A sum-of-products expression\text{A sum-of-products expression}

  4. AND-OR logic\text{AND-OR logic}

Show me the answer

Answer: 1. A product-of-sums expression\text{A product-of-sums expression}

Explanation:

  • Grouping 0s on a Karnaugh map produces a product-of-sums (POS) expression.

344. A 5-variable Karnaugh map has:

  1. Sixteen cells\text{Sixteen cells}

  2. Sixty-four cells\text{Sixty-four cells}

  3. Thirty-two cells\text{Thirty-two cells}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 3. Thirty-two cells\text{Thirty-two cells}

Explanation:

  • A 5-variable Karnaugh map has 25=322^5 = 32 cells.

345. The output expression for an AND-OR circuit having one AND gate with inputs A,B,C,DA, B, C, D and one AND gate with inputs E,FE, F is:

  1. ABCDEFABCDEF

  2. (A+B+C+D)(E+F)(A + B + C + D)(E + F)

  3. AFE+C+D+E+FAFE + C + D + E + F

  4. BCD+EFBCD + EF

Show me the answer

Answer: 4. BCD+EFBCD + EF

Explanation:

  • The output expression for the AND-OR circuit is BCD+EFBCD + EF.

346. A logic circuit with an output X=ABC+ACX = ABC + AC consists of:

  1. Two AND gates and one OR gate\text{Two AND gates and one OR gate}

  2. Two AND gates, one OR gate, and two inverters\text{Two AND gates, one OR gate, and two inverters}

  3. Two OR gates, one AND gate, and two inverters\text{Two OR gates, one AND gate, and two inverters}

  4. Two AND gates, one OR gate, and one inverter\text{Two AND gates, one OR gate, and one inverter}

Show me the answer

Answer: 1. Two AND gates and one OR gate\text{Two AND gates and one OR gate}

Explanation:

  • The expression X=ABC+ACX = ABC + AC requires two AND gates (for ABCABC and ACAC) and one OR gate.

347. To implement the expression ABCD+ABCD+ABCDABCD + ABCD + ABCD, it takes one OR gate and:

  1. One AND gate\text{One AND gate}

  2. Three AND gates and four inverters\text{Three AND gates and four inverters}

  3. Three AND gates\text{Three AND gates}

  4. Three AND gates and three inverters\text{Three AND gates and three inverters}

Show me the answer

Answer: 3. Three AND gates\text{Three AND gates}

Explanation:

  • The expression ABCD+ABCD+ABCDABCD + ABCD + ABCD requires three AND gates and one OR gate.

348. The expression ABCD+ABCD+ABCDABCD + ABCD + ABCD:

  1. Cannot be simplified\text{Cannot be simplified}

  2. Can be simplified to ABCD+ABC\text{Can be simplified to } ABCD + ABC

  3. Can be simplified to ABC+AB\text{Can be simplified to } ABC + AB

  4. None of these answers is correct\text{None of these answers is correct}

Show me the answer

Answer: 1. Cannot be simplified\text{Cannot be simplified}

Explanation:

  • The expression ABCD+ABCD+ABCDABCD + ABCD + ABCD is already in its simplest form and cannot be further simplified.

349. The input expression for an AND-OR-Invert circuit having one AND gate with inputs A,B,C,DA, B, C, D and one AND gate with inputs E,FE, F is:

  1. ABCD+EFABCD + EF

  2. A+B+C+D+E+FA + B + C + D + E + F

  3. (A+B+C+D)(E+F)(A + B + C + D)(E + F)

  4. (A+B+C+D)(E+F)(A + B + C + D)(E + F)

Show me the answer

Answer: 1. ABCD+EFABCD + EF

Explanation:

  • The input expression for the AND-OR-Invert circuit is ABCD+EFABCD + EF.

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