set-10
451. equal to
10
2.8
280
28
452. The binary number 1101 is equal to the decimal number
13
11
49
3
453. The binary number 11011101 is equal to the decimal number
121
441
221
256
454. The decimal number 17 is equal to the binary number
10010
10001
11000
01001
455. The decimal number 175 is equal to the binary number
11001111
10101111
10101110
11101111
456. The sum of 11010 + 01111 equals
101001
110101
101010
101000
457. The difference of 110 - 010 equals
001
101
010
100
458. The 1's complement of 10111001 is
01000111
11000110
01000110
10101010
459. The 2's complement of 11001000 is
00110111
01001000
00110001
00111000
460. The decimal number -34 is expressed in the 2's complement form as
01011110
11011110
10100010
01011101
461. The decimal number +122 is expressed in the 2's complement form as
01111010
01000101
11111010
10000101
462. A single-precision floating-point binary number has a total of
8 bits
24 bits
16 bits
32 bits
463. In the 2's complement form, the binary number 10010011 is equal to the decimal number
-19
+91
+109
-109
464. The binary number 101100111001010100001 can be written in hexadecimal as
5471238
2634521s
5471241s
23162501s
465. The binary number 10001101010001101111 can be written in hexadecimal as
466. The binary number for is
1111011110101001
1111111010110001
1110111110101001
1111011010101001
467. The BCD number for decimal 473 is
111011010
010001110011
110001110011
010011110011
468. Refer to Table 2-7. The word STOP in ASCII is
1010011101010010011111010000
1001010110110110011101010001
1010010100110010011101010000
1010011101010010011101100100
469. The number of parity bits to be added o an 8-bit word for constructing Hamming code for detection
1
3
2
4
470. A 7-bit Hamming code (even parity) 001001 for a BCD digit is known to have single error the encoded BCD digit is
9
3
5
0
471. When the input to an inverter is HIGH (I), the output is
HIGH or 1
HIGH or 0
LOW or 1
LOW or 0
472. An inverter performs an operation known as
Complementation
Inversion
Assertion
Both answers (A) and (B)
473. The output of an AND gate with inputs A, B, and C is a 1 (HIGH) when
A = 1, B = 1, C = 1
A = 0, B = 0, C = 0
A = 1, B = 0, C = 1
Only answers (A) and (C)
474. A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3ms. The output pulse can be described as follows:
It goes LOW at t = 0 and back HIGH at t = 3ms
It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms
It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms
It goes LOW at t = 0.8 ms and back LOW at t = 1 ms
475. A pulse is applied to each input of a 2-input NOR gate, one pulse goes HIGH at t = 0 and goes back LOW at t = 1ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:
It goes LOW at t = 0 and back HIGH at t = 3 ms.
It goes LOW at t = 0.8 ms and back HIGH at t = 3ms
It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms
It goes HIGH at t = 0.8 ms and back LOW at t = 1 ms
476. A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:
It goes HIGH at t = 0 and back LOW at t = 3 ms
It goes HIGH at t = 0 and back LOW at t = 0.8ms
It goes HIGH at t = .1 ms and back LOW at t = 3ms
Both answers (B) and (C)
477. For and AND gate
All LOW input produce a HIGH output
Output is HIGH if and only if all inputs are HIGH
Output is LOW if and only if all inputs are HIGH
Output is LOW if and only if all inputs are LOW
478. The output of a gate is LOW when atleast one of its inputs is HIGH. This is true for
AND
OR
NAND
NOR
479. The output of a gate is LOW when atleast one of its inputs is LOW. It is true for
AND
NAND
OR
NOR
480. The output of a gate is HIGH when atleast one of its inputs is LOW. It is true for
XOR
NOR
NAND
OR
481. The output of a gate is HIGH when atleast one of its inputs is HIGH. It is true for
NAND
OR
AND
XOR
482. The output of a gate is HIGH if and only if all its inputs are HIGH. It is true for
XOR
OR
AND
NAND
483. The output of a gate is LOW if and only if all its inputs are HIGH. It is true for
AND
NOR
XNOR
NAND
484. The output of a gate is HIGH if and only if all its inputs are LOW. It is true for
NOR
NAND
XOR
XNOR
485. The output of a gate is LOW if and only if all its inputs are LOW. It is true for
XOR
OR
AND
NOR
486. The output of a 2-input gates is 1 if and only if its inputs are unequal. It is true for
OR
XNOR
XOR
NOR
487. The output of a 2-input gates is 0 if and only if its inputs are unequal. It is true for
XNOR
NOR
AND
NAND
488. The output of a 2-input gates is 1 if and only if its inputs are equal. It is true for
AND
OR
XOR
XNOR
489. The output of a 2-input gates is 0 if and only if its inputs are unequal. It is true for
AND
OR
XOR
NOR
490. The most suitable gate for comparing two bits is
AND
NAND
OR
XOR
491. Which of the following gates can be used as an inverter?
AND
XOR
OR
None of the above
492. Which of the following gates cannot be used as an inverter?
NAND
NOR
AND
XNOR
493. The maximum number of 3-inputs gates in a 16-pin IC will be
2
4
3
5
494. A quality having continuous values is
A digital quantity
A binary quantity
An analog quantity
A natural quantity
495. The term bit means
A small amount of data
Binary digit
A 1 or a 0
Both answers (B) and (C)
496. The time interval on the leading edge of a pulse between 10% and 90% of the amplitude is the
Rise time
Pulse width
Fall time
Period
497. A pulse in a certain waveform occurs every 10 ms. The frequency is
1 kHz
100Hz
1 Hz
10 Hz
498. In a certain digital waveform, the period is twice the pulse width. The duty cycle is
100%
50%
200%
150%
499. An inverter
Performs the NOT operation
Changes a LOW to a HIGH
Changes a HIGH to a LOW
Does all of the above
500. The output of an AND gate is HIGH when
Any input is HIGH
No inputs are HIGH
All inputs are HIGH
Both answers (A) and (C)
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