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301. The output of an SR flip-flop when S=1S = 1S=1 and R=0R = 0R=0 is:

  1. 111

  2. No change\text{No change}No change

  3. 000

  4. High impedance\text{High impedance}High impedance

Show me the answer

Answer: 1. 111

Explanation:

  • When S=1S = 1S=1 and R=0R = 0R=0, the SR flip-flop sets the output to 111.

302. The number of flip-flops contained in IC 7490 is:

  1. 222

  2. 444

  3. 333

  4. 101010

Show me the answer

Answer: 2. 444

Explanation:

  • The IC 7490 contains 4 flip-flops.

303. The number of control lines for a 32-to-1 multiplexer is:

Show me the answer

Explanation:

Show me the answer

Explanation:

305. Which of the following cannot be accessed randomly?

Show me the answer

Explanation:

  • Magnetic tape is a sequential access memory and cannot be accessed randomly.

306. The excess-3 code of decimal 7 is represented by:

Show me the answer

Explanation:

Show me the answer

Explanation:

308. The result of adding the hexadecimal number A6 to 3A is:

Show me the answer

Explanation:

309. A universal logic gate is one that can be used to generate any logic function. Which of the following is a universal logic gate?

Show me the answer

Explanation:

  • NAND gates are universal because they can be used to implement any logic function.

310. The logic 0 level of a CMOS logic device is approximately:

Show me the answer

Explanation:

311. A Karnaugh map is used for the purpose of:

Show me the answer

Explanation:

  • Karnaugh maps are used to simplify Boolean expressions by minimizing the number of terms.

312. A full adder logic circuit will have:

Show me the answer

Explanation:

  • A full adder has three inputs (A, B, and carry-in) and two outputs (sum and carry-out).

313. An eight-stage ripple counter uses flip-flops with a propagation delay of 75 nanoseconds each. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately:

Show me the answer

Explanation:

314. The output of a JK flip-flop with asynchronous preset and clear inputs is '1'. The output can be changed to '0' with one of the following conditions:

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Explanation:

315. The information in ROM is stored:

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Explanation:

  • ROM (Read-Only Memory) is programmed by the manufacturer and cannot be modified by the user.

316. The conversion speed of an analog-to-digital converter is maximum with the following technique:

Show me the answer

Explanation:

  • Parallel comparator A/D converters have the fastest conversion speed.

317. A weighted resistor digital-to-analog converter using N bits requires a total of:

Show me the answer

Explanation:

  • A weighted resistor DAC requires one precision resistor for each bit.

318. The 2's complement of the number 1101110 is:

Show me the answer

Explanation:

319. The decimal equivalent of the binary number 10101 is:

Show me the answer

Explanation:

Show me the answer

Explanation:

321. How many select lines will a 32-to-1 multiplexer have?

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Explanation:

322. How many address bits are required to represent 4K memory?

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Explanation:

Show me the answer

Explanation:

324. Which of the following are known as universal gates?

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Explanation:

  • NAND and NOR gates are universal because they can be used to implement any logic function.

325. Which of the following memories stores the most number of bits?

Show me the answer

Explanation:

326. Which of the following consumes minimum power?

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Explanation:

  • CMOS logic consumes the least power among the given options.

327. The complement of a variable is always:

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Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

331. According to the commutative law of addition:

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Explanation:

332. According to the associative law of multiplication:

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Explanation:

333. According to the distributive law:

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Explanation:

334. Which one of the following is not a valid rule of Boolean algebra?

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Explanation:

335. Which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?

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Explanation:

336. According to De Morgan’s theorems, the following equality(s) are correct:

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Explanation:

  • De Morgan’s theorems state that:

  • All the given equalities are correct.

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Explanation:

338. An example of a sum-of-products expression is:

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Explanation:

339. An example of a sum-of-sums expression is:

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Explanation:

340. An example of a standard SOP expression is:

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Explanation:

341. A 3-variable Karnaugh map has:

Show me the answer

Explanation:

342. In a 4-variable Karnaugh map, a 2-variable product term is produced by:

Show me the answer

Explanation:

  • A 2-variable product term is produced by a 4-cell group of 1s in a 4-variable Karnaugh map.

343. On a Karnaugh map, grouping the 0s produces:

Show me the answer

Explanation:

  • Grouping 0s on a Karnaugh map produces a product-of-sums (POS) expression.

344. A 5-variable Karnaugh map has:

Show me the answer

Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

Show me the answer

Explanation:

444

161616

555

666

Answer: 3. 555

A 32-to-1 multiplexer requires 555 control lines because 25=322^5 = 3225=32.

304. How many two-input AND & OR gates are required to realize Y=CD+EF+GY = CD + EF + GY=CD+EF+G?

2,22, 22,2

3,33, 33,3

2,32, 32,3

None of these\text{None of these}None of these

Answer: 1. 2,22, 22,2

Two AND gates are required for CDCDCD and EFEFEF, and two OR gates are required for combining the terms.

DRAM\text{DRAM}DRAM

ROM\text{ROM}ROM

SRAM\text{SRAM}SRAM

Magnetic tape\text{Magnetic tape}Magnetic tape

Answer: 4. Magnetic tape\text{Magnetic tape}Magnetic tape

110011001100

101110111011

100110011001

101010101010

Answer: 2. 101110111011

The excess-3 code of 7 is obtained by adding 3 to 7, resulting in 101010, which is 101010101010 in binary.

307. When an input signal A=11001A = 11001A=11001 is applied to a NOT gate serially, its output signal is:

001110011100111

101011010110101

001100011000110

110011100111001

Answer: 3. 001100011000110

The NOT gate inverts each bit of the input signal, so 110011100111001 becomes 001100011000110.

DDDDDD

F0F0F0

E0E0E0

EFEFEF

Answer: 3. E0E0E0

Adding A6 (166166166 in decimal) and 3A (585858 in decimal) gives E0 (224224224 in decimal).

OR\text{OR}OR

XOR\text{XOR}XOR

AND\text{AND}AND

NAND\text{NAND}NAND

Answer: 4. NAND\text{NAND}NAND

1.2 volts1.2 \text{ volts}1.2 volts

5 volts5 \text{ volts}5 volts

0.4 volts0.4 \text{ volts}0.4 volts

0 volts0 \text{ volts}0 volts

Answer: 4. 0 volts0 \text{ volts}0 volts

In CMOS logic, a logic 0 is represented by a voltage close to 000 volts.

Reducing the electronic circuits used\text{Reducing the electronic circuits used}Reducing the electronic circuits used

Mapping the given Boolean logic function\text{Mapping the given Boolean logic function}Mapping the given Boolean logic function

Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}Minimizing the terms in a Boolean expression

Maximizing the terms of a given Boolean expression\text{Maximizing the terms of a given Boolean expression}Maximizing the terms of a given Boolean expression

Answer: 3. Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}Minimizing the terms in a Boolean expression

Two inputs and one output\text{Two inputs and one output}Two inputs and one output

Three inputs and three outputs\text{Three inputs and three outputs}Three inputs and three outputs

Two inputs and two outputs\text{Two inputs and two outputs}Two inputs and two outputs

Three inputs and two outputs\text{Three inputs and two outputs}Three inputs and two outputs

Answer: 4. Three inputs and two outputs\text{Three inputs and two outputs}Three inputs and two outputs

1 MHz1 \text{ MHz}1 MHz

2 MHz2 \text{ MHz}2 MHz

500 MHz500 \text{ MHz}500 MHz

4 MHz4 \text{ MHz}4 MHz

Answer: 1. 1 MHz1 \text{ MHz}1 MHz

The maximum frequency is determined by the total propagation delay, which is 8×75 ns=600 ns8 \times 75 \text{ ns} = 600 \text{ ns}8×75 ns=600 ns. The frequency is 1/600 ns≈1.67 MHz1 / 600 \text{ ns} \approx 1.67 \text{ MHz}1/600 ns≈1.67 MHz, so 1 MHz is the closest option.

By applying J=0,K=0 and using a clock\text{By applying } J = 0, K = 0 \text{ and using a clock}By applying J=0,K=0 and using a clock

By applying J=1,K=0 and using the clock\text{By applying } J = 1, K = 0 \text{ and using the clock}By applying J=1,K=0 and using the clock

By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}By applying J=1,K=1 and using the clock

By applying a synchronous preset input\text{By applying a synchronous preset input}By applying a synchronous preset input

Answer: 3. By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}By applying J=1,K=1 and using the clock

When J=1J = 1J=1 and K=1K = 1K=1, the JK flip-flop toggles its output on the clock pulse, changing it from 1 to 0.

By the user any number of times\text{By the user any number of times}By the user any number of times

By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}By the manufacturer during fabrication of the device

By the user using ultraviolet light\text{By the user using ultraviolet light}By the user using ultraviolet light

By the user once and only once\text{By the user once and only once}By the user once and only once

Answer: 2. By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}By the manufacturer during fabrication of the device

Dual slope A/D converter\text{Dual slope A/D converter}Dual slope A/D converter

Serial comparator A/D converter\text{Serial comparator A/D converter}Serial comparator A/D converter

Successive approximation A/D converter\text{Successive approximation A/D converter}Successive approximation A/D converter

Parallel comparator A/D converter\text{Parallel comparator A/D converter}Parallel comparator A/D converter

Answer: 4. Parallel comparator A/D converter\text{Parallel comparator A/D converter}Parallel comparator A/D converter

N precision resistorsN \text{ precision resistors}N precision resistors

N+1 precision resistorsN + 1 \text{ precision resistors}N+1 precision resistors

2N precision resistors2N \text{ precision resistors}2N precision resistors

N−1 precision resistorsN - 1 \text{ precision resistors}N−1 precision resistors

Answer: 1. N precision resistorsN \text{ precision resistors}N precision resistors

001000100100010010001

001001000100100010010

001000100100010010001

None\text{None}None

Answer: 2. 001001000100100010010

The 2's complement of 1101110 is obtained by inverting the bits and adding 1, resulting in 001001000100100010010.

212121

262626

313131

282828

Answer: 1. 212121

The binary number 101011010110101 converts to the decimal number 212121.

320. How many two-input AND gates and two-input OR gates are required to realize Y=BD+CE+ABY = BD + CE + ABY=BD+CE+AB?

1,11, 11,1

3,23, 23,2

4,24, 24,2

2,32, 32,3

Answer: 2. 3,23, 23,2

Three AND gates are required for BDBDBD, CECECE, and ABABAB, and two OR gates are required for combining the terms.

555

999

888

111111

Answer: 1. 555

A 32-to-1 multiplexer requires 555 select lines because 25=322^5 = 3225=32.

5 bits5 \text{ bits}5 bits

8 bits8 \text{ bits}8 bits

12 bits12 \text{ bits}12 bits

10 bits10 \text{ bits}10 bits

Answer: 3. 12 bits12 \text{ bits}12 bits

A 4K memory requires log⁡2(4096)=12\log_2(4096) = 12log2​(4096)=12 address bits.

323. For a JK flip-flop with J=0J = 0J=0 and K=1K = 1K=1, the output after a clock pulse will be:

111

000

No change\text{No change}No change

High impedance\text{High impedance}High impedance

Answer: 2. 000

When J=0J = 0J=0 and K=1K = 1K=1, the JK flip-flop resets the output to 000.

NAND and NOR\text{NAND and NOR}NAND and NOR

XOR and OR\text{XOR and OR}XOR and OR

AND and OR\text{AND and OR}AND and OR

None\text{None}None

Answer: 1. NAND and NOR\text{NAND and NOR}NAND and NOR

64Kx8 memory\text{64Kx8 memory}64Kx8 memory

32Mx8 memory\text{32Mx8 memory}32Mx8 memory

1Mx8 memory\text{1Mx8 memory}1Mx8 memory

64x6 memory\text{64x6 memory}64x6 memory

Answer: 2. 32Mx8 memory\text{32Mx8 memory}32Mx8 memory

A 32Mx8 memory stores 32×8=25632 \times 8 = 25632×8=256 million bits, which is the largest among the options.

TTL\text{TTL}TTL

DTL\text{DTL}DTL

CMOS\text{CMOS}CMOS

RTL\text{RTL}RTL

Answer: 3. CMOS\text{CMOS}CMOS

000

Equal to the variable\text{Equal to the variable}Equal to the variable

111

The inverse of the variable\text{The inverse of the variable}The inverse of the variable

Answer: 4. The inverse of the variable\text{The inverse of the variable}The inverse of the variable

The complement of a variable is its inverse (e.g., A‾\overline{A}A).

328. The Boolean expression A+B+CA + B + CA+B+C is:

A sum term\text{A sum term}A sum term

A product term\text{A product term}A product term

A literal term\text{A literal term}A literal term

A complement term\text{A complement term}A complement term

Answer: 1. A sum term\text{A sum term}A sum term

The expression A+B+CA + B + CA+B+C is a sum term because it represents the logical OR of the variables.

329. The Boolean expression AB′CD′AB'CD'AB′CD′ is:

A sum term\text{A sum term}A sum term

A literal\text{A literal}A literal

A product term\text{A product term}A product term

Always 1\text{Always 1}Always 1

Answer: 3. A product term\text{A product term}A product term

The expression AB′CD′AB'CD'AB′CD′ is a product term because it represents the logical AND of the variables.

330. The domain of the expression AB′CD+AB′+C′D+BAB'CD + AB' + C'D + BAB′CD+AB′+C′D+B is:

A and DA \text{ and } DA and D

A,B,C, and DA, B, C, \text{ and } DA,B,C, and D

B onlyB \text{ only}B only

None of the above\text{None of the above}None of the above

Answer: 2. A,B,C, and DA, B, C, \text{ and } DA,B,C, and D

The domain of the expression includes all variables A,B,C, and DA, B, C, \text{ and } DA,B,C, and D.

AB=BAAB = BAAB=BA

A+(B+C)=(A+B)+CA + (B + C) = (A + B) + CA+(B+C)=(A+B)+C

A=A+AA = A + AA=A+A

A+B=B+AA + B = B + AA+B=B+A

Answer: 4. A+B=B+AA + B = B + AA+B=B+A

The commutative law of addition states that the order of operands does not affect the result, so A+B=B+AA + B = B + AA+B=B+A.

B=BBB = BBB=BB

A+B=B+AA + B = B + AA+B=B+A

A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

B+B(B+0)B + B(B + 0)B+B(B+0)

Answer: 3. A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

The associative law of multiplication states that the grouping of operands does not affect the result, so A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C.

A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC

A(A+1)=AA(A + 1) = AA(A+1)=A

A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

A+AB=AA + AB = AA+AB=A

Answer: 1. A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC

The distributive law states that multiplication distributes over addition, so A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC.

A+1=1A + 1 = 1A+1=1

AA=AAA = AAA=A

A=AA = AA=A

A+0=AA + 0 = AA+0=A

Answer: 3. A=AA = AA=A

The statement A=AA = AA=A is not a rule of Boolean algebra; it is an identity.

A+1=1A + 1 = 1A+1=1

AA=AAA = AAA=A

A+A=AA + A = AA+A=A

A⋅1=AA \cdot 1 = AA⋅1=A

Answer: 4. A⋅1=AA \cdot 1 = AA⋅1=A

The rule A⋅1=AA \cdot 1 = AA⋅1=A states that if one input of an AND gate is 1, the output is equal to the other input.

AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}AB=A+B

A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}A+B+C​=A⋅B⋅C

XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}XYZ=X+Y+Z

All of the above\text{All of the above}All of the above

Answer: 4. All of the above\text{All of the above}All of the above

AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}AB=A+B

A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}A+B+C​=A⋅B⋅C

XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}XYZ=X+Y+Z

337. The Boolean expression X=AB+CDX = AB + CDX=AB+CD represents:

Two ORs ANDed together\text{Two ORs ANDed together}Two ORs ANDed together

Two ANDs ORed together\text{Two ANDs ORed together}Two ANDs ORed together

A 4-input AND gate\text{A 4-input AND gate}A 4-input AND gate

An exclusive-OR\text{An exclusive-OR}An exclusive-OR

Answer: 2. Two ANDs ORed together\text{Two ANDs ORed together}Two ANDs ORed together

The expression X=AB+CDX = AB + CDX=AB+CD represents two AND gates (ABABAB and CDCDCD) whose outputs are ORed together.

A+B(C+D)A + B(C + D)A+B(C+D)

AB+AC+ABCAB + AC + ABCAB+AC+ABC

(A+B+C)(A+B+C)(A + B + C)(A + B + C)(A+B+C)(A+B+C)

Both answers A and B\text{Both answers A and B}Both answers A and B

Answer: 2. AB+AC+ABCAB + AC + ABCAB+AC+ABC

A sum-of-products expression is a logical OR of multiple AND terms, such as AB+AC+ABCAB + AC + ABCAB+AC+ABC.

A(B+C)+AGA(B + C) + AGA(B+C)+AG

A+B+BCA + B + BCA+B+BC

(A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C)

Both answers A and B\text{Both answers A and B}Both answers A and B

Answer: 3. (A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C)

A sum-of-sums expression is a logical AND of multiple OR terms, such as (A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C).

AB+ABC+ABDAB + ABC + ABDAB+ABC+ABD

AB+AB+ABAB + AB + ABAB+AB+AB

ABC+ACDABC + ACDABC+ACD

ABCD+AB+AABCD + AB + AABCD+AB+A

Answer: 3. ABC+ACDABC + ACDABC+ACD

A standard SOP (Sum of Products) expression consists of AND terms combined with OR, such as ABC+ACDABC + ACDABC+ACD.

Eight cells\text{Eight cells}Eight cells

Sixteen cells\text{Sixteen cells}Sixteen cells

Three cells\text{Three cells}Three cells

Four cells\text{Four cells}Four cells

Answer: 1. Eight cells\text{Eight cells}Eight cells

A 3-variable Karnaugh map has 23=82^3 = 823=8 cells.

A 2-cell group of 1s\text{A 2-cell group of 1s}A 2-cell group of 1s

A 4-cell group of 1s\text{A 4-cell group of 1s}A 4-cell group of 1s

An 8-cell group of 1s\text{An 8-cell group of 1s}An 8-cell group of 1s

A 4-cell group of 0s\text{A 4-cell group of 0s}A 4-cell group of 0s

Answer: 2. A 4-cell group of 1s\text{A 4-cell group of 1s}A 4-cell group of 1s

A product-of-sums expression\text{A product-of-sums expression}A product-of-sums expression

A "don’t care" condition\text{A "don’t care" condition}A "don’t care" condition

A sum-of-products expression\text{A sum-of-products expression}A sum-of-products expression

AND-OR logic\text{AND-OR logic}AND-OR logic

Answer: 1. A product-of-sums expression\text{A product-of-sums expression}A product-of-sums expression

Sixteen cells\text{Sixteen cells}Sixteen cells

Sixty-four cells\text{Sixty-four cells}Sixty-four cells

Thirty-two cells\text{Thirty-two cells}Thirty-two cells

All of the above\text{All of the above}All of the above

Answer: 3. Thirty-two cells\text{Thirty-two cells}Thirty-two cells

A 5-variable Karnaugh map has 25=322^5 = 3225=32 cells.

345. The output expression for an AND-OR circuit having one AND gate with inputs A,B,C,DA, B, C, DA,B,C,D and one AND gate with inputs E,FE, FE,F is:

ABCDEFABCDEFABCDEF

(A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

AFE+C+D+E+FAFE + C + D + E + FAFE+C+D+E+F

BCD+EFBCD + EFBCD+EF

Answer: 4. BCD+EFBCD + EFBCD+EF

The output expression for the AND-OR circuit is BCD+EFBCD + EFBCD+EF.

346. A logic circuit with an output X=ABC+ACX = ABC + ACX=ABC+AC consists of:

Two AND gates and one OR gate\text{Two AND gates and one OR gate}Two AND gates and one OR gate

Two AND gates, one OR gate, and two inverters\text{Two AND gates, one OR gate, and two inverters}Two AND gates, one OR gate, and two inverters

Two OR gates, one AND gate, and two inverters\text{Two OR gates, one AND gate, and two inverters}Two OR gates, one AND gate, and two inverters

Two AND gates, one OR gate, and one inverter\text{Two AND gates, one OR gate, and one inverter}Two AND gates, one OR gate, and one inverter

Answer: 1. Two AND gates and one OR gate\text{Two AND gates and one OR gate}Two AND gates and one OR gate

The expression X=ABC+ACX = ABC + ACX=ABC+AC requires two AND gates (for ABCABCABC and ACACAC) and one OR gate.

347. To implement the expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD, it takes one OR gate and:

One AND gate\text{One AND gate}One AND gate

Three AND gates and four inverters\text{Three AND gates and four inverters}Three AND gates and four inverters

Three AND gates\text{Three AND gates}Three AND gates

Three AND gates and three inverters\text{Three AND gates and three inverters}Three AND gates and three inverters

Answer: 3. Three AND gates\text{Three AND gates}Three AND gates

The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD requires three AND gates and one OR gate.

348. The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD:

Cannot be simplified\text{Cannot be simplified}Cannot be simplified

Can be simplified to ABCD+ABC\text{Can be simplified to } ABCD + ABCCan be simplified to ABCD+ABC

Can be simplified to ABC+AB\text{Can be simplified to } ABC + ABCan be simplified to ABC+AB

None of these answers is correct\text{None of these answers is correct}None of these answers is correct

Answer: 1. Cannot be simplified\text{Cannot be simplified}Cannot be simplified

The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD is already in its simplest form and cannot be further simplified.

349. The input expression for an AND-OR-Invert circuit having one AND gate with inputs A,B,C,DA, B, C, DA,B,C,D and one AND gate with inputs E,FE, FE,F is:

ABCD+EFABCD + EFABCD+EF

A+B+C+D+E+FA + B + C + D + E + FA+B+C+D+E+F

(A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

(A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

Answer: 1. ABCD+EFABCD + EFABCD+EF

The input expression for the AND-OR-Invert circuit is ABCD+EFABCD + EFABCD+EF.