computer-nec-license
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  • 1. Concept of Basic Electrical and Electronics Engineering
    • 1.1 Basic Concepts
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    • 2.1 Digital Logic
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    • 3.1 Introduction to C Programming
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    • 6.1 Introduction to Finite Automata
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    • 7.1 Introduction to Data Structures, Lists, Linked Lists, and Trees
    • 7.2 Sorting, Searching, Hashing and Graphs
    • 7.3 Introduction to Data Models, Normalization, and SQL
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    • 8.1 Software Process and Requirements
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    • 9.1 Introduction to AI and Intelligent Agents
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    • 10.1 Engineering Drawings and Its Concepts
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  1. 2. Digital Logic and Microprocessor
  2. MCQs
  3. MCQs On Digital Logic

set-7

301. The output of an SR flip-flop when S=1S = 1S=1 and R=0R = 0R=0 is:

  1. 111

  2. No change\text{No change}No change

  3. 000

  4. High impedance\text{High impedance}High impedance

Show me the answer

Answer: 1. 111

Explanation:

  • When S=1S = 1S=1 and R=0R = 0R=0, the SR flip-flop sets the output to 111.

302. The number of flip-flops contained in IC 7490 is:

  1. 222

  2. 444

  3. 333

  4. 101010

Show me the answer

Answer: 2. 444

Explanation:

  • The IC 7490 contains 4 flip-flops.

303. The number of control lines for a 32-to-1 multiplexer is:

  1. 444

  2. 161616

  3. 555

  4. 666

Show me the answer

Answer: 3. 555

Explanation:

  • A 32-to-1 multiplexer requires 555 control lines because 25=322^5 = 3225=32.

304. How many two-input AND & OR gates are required to realize Y=CD+EF+GY = CD + EF + GY=CD+EF+G?

  1. 2,22, 22,2

  2. 3,33, 33,3

  3. 2,32, 32,3

  4. None of these\text{None of these}None of these

Show me the answer

Answer: 1. 2,22, 22,2

Explanation:

  • Two AND gates are required for CDCDCD and EFEFEF, and two OR gates are required for combining the terms.

305. Which of the following cannot be accessed randomly?

  1. DRAM\text{DRAM}DRAM

  2. ROM\text{ROM}ROM

  3. SRAM\text{SRAM}SRAM

  4. Magnetic tape\text{Magnetic tape}Magnetic tape

Show me the answer

Answer: 4. Magnetic tape\text{Magnetic tape}Magnetic tape

Explanation:

  • Magnetic tape is a sequential access memory and cannot be accessed randomly.

306. The excess-3 code of decimal 7 is represented by:

  1. 110011001100

  2. 101110111011

  3. 100110011001

  4. 101010101010

Show me the answer

Answer: 2. 101110111011

Explanation:

  • The excess-3 code of 7 is obtained by adding 3 to 7, resulting in 101010, which is 101010101010 in binary.

307. When an input signal A=11001A = 11001A=11001 is applied to a NOT gate serially, its output signal is:

  1. 001110011100111

  2. 101011010110101

  3. 001100011000110

  4. 110011100111001

Show me the answer

Answer: 3. 001100011000110

Explanation:

  • The NOT gate inverts each bit of the input signal, so 110011100111001 becomes 001100011000110.

308. The result of adding the hexadecimal number A6 to 3A is:

  1. DDDDDD

  2. F0F0F0

  3. E0E0E0

  4. EFEFEF

Show me the answer

Answer: 3. E0E0E0

Explanation:

  • Adding A6 (166166166 in decimal) and 3A (585858 in decimal) gives E0 (224224224 in decimal).

309. A universal logic gate is one that can be used to generate any logic function. Which of the following is a universal logic gate?

  1. OR\text{OR}OR

  2. XOR\text{XOR}XOR

  3. AND\text{AND}AND

  4. NAND\text{NAND}NAND

Show me the answer

Answer: 4. NAND\text{NAND}NAND

Explanation:

  • NAND gates are universal because they can be used to implement any logic function.

310. The logic 0 level of a CMOS logic device is approximately:

  1. 1.2 volts1.2 \text{ volts}1.2 volts

  2. 5 volts5 \text{ volts}5 volts

  3. 0.4 volts0.4 \text{ volts}0.4 volts

  4. 0 volts0 \text{ volts}0 volts

Show me the answer

Answer: 4. 0 volts0 \text{ volts}0 volts

Explanation:

  • In CMOS logic, a logic 0 is represented by a voltage close to 000 volts.

311. A Karnaugh map is used for the purpose of:

  1. Reducing the electronic circuits used\text{Reducing the electronic circuits used}Reducing the electronic circuits used

  2. Mapping the given Boolean logic function\text{Mapping the given Boolean logic function}Mapping the given Boolean logic function

  3. Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}Minimizing the terms in a Boolean expression

  4. Maximizing the terms of a given Boolean expression\text{Maximizing the terms of a given Boolean expression}Maximizing the terms of a given Boolean expression

Show me the answer

Answer: 3. Minimizing the terms in a Boolean expression\text{Minimizing the terms in a Boolean expression}Minimizing the terms in a Boolean expression

Explanation:

  • Karnaugh maps are used to simplify Boolean expressions by minimizing the number of terms.

312. A full adder logic circuit will have:

  1. Two inputs and one output\text{Two inputs and one output}Two inputs and one output

  2. Three inputs and three outputs\text{Three inputs and three outputs}Three inputs and three outputs

  3. Two inputs and two outputs\text{Two inputs and two outputs}Two inputs and two outputs

  4. Three inputs and two outputs\text{Three inputs and two outputs}Three inputs and two outputs

Show me the answer

Answer: 4. Three inputs and two outputs\text{Three inputs and two outputs}Three inputs and two outputs

Explanation:

  • A full adder has three inputs (A, B, and carry-in) and two outputs (sum and carry-out).

313. An eight-stage ripple counter uses flip-flops with a propagation delay of 75 nanoseconds each. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately:

  1. 1 MHz1 \text{ MHz}1 MHz

  2. 2 MHz2 \text{ MHz}2 MHz

  3. 500 MHz500 \text{ MHz}500 MHz

  4. 4 MHz4 \text{ MHz}4 MHz

Show me the answer

Answer: 1. 1 MHz1 \text{ MHz}1 MHz

Explanation:

  • The maximum frequency is determined by the total propagation delay, which is 8×75 ns=600 ns8 \times 75 \text{ ns} = 600 \text{ ns}8×75 ns=600 ns. The frequency is 1/600 ns≈1.67 MHz1 / 600 \text{ ns} \approx 1.67 \text{ MHz}1/600 ns≈1.67 MHz, so 1 MHz is the closest option.

314. The output of a JK flip-flop with asynchronous preset and clear inputs is '1'. The output can be changed to '0' with one of the following conditions:

  1. By applying J=0,K=0 and using a clock\text{By applying } J = 0, K = 0 \text{ and using a clock}By applying J=0,K=0 and using a clock

  2. By applying J=1,K=0 and using the clock\text{By applying } J = 1, K = 0 \text{ and using the clock}By applying J=1,K=0 and using the clock

  3. By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}By applying J=1,K=1 and using the clock

  4. By applying a synchronous preset input\text{By applying a synchronous preset input}By applying a synchronous preset input

Show me the answer

Answer: 3. By applying J=1,K=1 and using the clock\text{By applying } J = 1, K = 1 \text{ and using the clock}By applying J=1,K=1 and using the clock

Explanation:

  • When J=1J = 1J=1 and K=1K = 1K=1, the JK flip-flop toggles its output on the clock pulse, changing it from 1 to 0.

315. The information in ROM is stored:

  1. By the user any number of times\text{By the user any number of times}By the user any number of times

  2. By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}By the manufacturer during fabrication of the device

  3. By the user using ultraviolet light\text{By the user using ultraviolet light}By the user using ultraviolet light

  4. By the user once and only once\text{By the user once and only once}By the user once and only once

Show me the answer

Answer: 2. By the manufacturer during fabrication of the device\text{By the manufacturer during fabrication of the device}By the manufacturer during fabrication of the device

Explanation:

  • ROM (Read-Only Memory) is programmed by the manufacturer and cannot be modified by the user.

316. The conversion speed of an analog-to-digital converter is maximum with the following technique:

  1. Dual slope A/D converter\text{Dual slope A/D converter}Dual slope A/D converter

  2. Serial comparator A/D converter\text{Serial comparator A/D converter}Serial comparator A/D converter

  3. Successive approximation A/D converter\text{Successive approximation A/D converter}Successive approximation A/D converter

  4. Parallel comparator A/D converter\text{Parallel comparator A/D converter}Parallel comparator A/D converter

Show me the answer

Answer: 4. Parallel comparator A/D converter\text{Parallel comparator A/D converter}Parallel comparator A/D converter

Explanation:

  • Parallel comparator A/D converters have the fastest conversion speed.

317. A weighted resistor digital-to-analog converter using N bits requires a total of:

  1. N precision resistorsN \text{ precision resistors}N precision resistors

  2. N+1 precision resistorsN + 1 \text{ precision resistors}N+1 precision resistors

  3. 2N precision resistors2N \text{ precision resistors}2N precision resistors

  4. N−1 precision resistorsN - 1 \text{ precision resistors}N−1 precision resistors

Show me the answer

Answer: 1. N precision resistorsN \text{ precision resistors}N precision resistors

Explanation:

  • A weighted resistor DAC requires one precision resistor for each bit.

318. The 2's complement of the number 1101110 is:

  1. 001000100100010010001

  2. 001001000100100010010

  3. 001000100100010010001

  4. None\text{None}None

Show me the answer

Answer: 2. 001001000100100010010

Explanation:

  • The 2's complement of 1101110 is obtained by inverting the bits and adding 1, resulting in 001001000100100010010.

319. The decimal equivalent of the binary number 10101 is:

  1. 212121

  2. 262626

  3. 313131

  4. 282828

Show me the answer

Answer: 1. 212121

Explanation:

  • The binary number 101011010110101 converts to the decimal number 212121.

320. How many two-input AND gates and two-input OR gates are required to realize Y=BD+CE+ABY = BD + CE + ABY=BD+CE+AB?

  1. 1,11, 11,1

  2. 3,23, 23,2

  3. 4,24, 24,2

  4. 2,32, 32,3

Show me the answer

Answer: 2. 3,23, 23,2

Explanation:

  • Three AND gates are required for BDBDBD, CECECE, and ABABAB, and two OR gates are required for combining the terms.

321. How many select lines will a 32-to-1 multiplexer have?

  1. 555

  2. 999

  3. 888

  4. 111111

Show me the answer

Answer: 1. 555

Explanation:

  • A 32-to-1 multiplexer requires 555 select lines because 25=322^5 = 3225=32.

322. How many address bits are required to represent 4K memory?

  1. 5 bits5 \text{ bits}5 bits

  2. 8 bits8 \text{ bits}8 bits

  3. 12 bits12 \text{ bits}12 bits

  4. 10 bits10 \text{ bits}10 bits

Show me the answer

Answer: 3. 12 bits12 \text{ bits}12 bits

Explanation:

  • A 4K memory requires log⁡2(4096)=12\log_2(4096) = 12log2​(4096)=12 address bits.

323. For a JK flip-flop with J=0J = 0J=0 and K=1K = 1K=1, the output after a clock pulse will be:

  1. 111

  2. 000

  3. No change\text{No change}No change

  4. High impedance\text{High impedance}High impedance

Show me the answer

Answer: 2. 000

Explanation:

  • When J=0J = 0J=0 and K=1K = 1K=1, the JK flip-flop resets the output to 000.

324. Which of the following are known as universal gates?

  1. NAND and NOR\text{NAND and NOR}NAND and NOR

  2. XOR and OR\text{XOR and OR}XOR and OR

  3. AND and OR\text{AND and OR}AND and OR

  4. None\text{None}None

Show me the answer

Answer: 1. NAND and NOR\text{NAND and NOR}NAND and NOR

Explanation:

  • NAND and NOR gates are universal because they can be used to implement any logic function.

325. Which of the following memories stores the most number of bits?

  1. 64Kx8 memory\text{64Kx8 memory}64Kx8 memory

  2. 32Mx8 memory\text{32Mx8 memory}32Mx8 memory

  3. 1Mx8 memory\text{1Mx8 memory}1Mx8 memory

  4. 64x6 memory\text{64x6 memory}64x6 memory

Show me the answer

Answer: 2. 32Mx8 memory\text{32Mx8 memory}32Mx8 memory

Explanation:

  • A 32Mx8 memory stores 32×8=25632 \times 8 = 25632×8=256 million bits, which is the largest among the options.

326. Which of the following consumes minimum power?

  1. TTL\text{TTL}TTL

  2. DTL\text{DTL}DTL

  3. CMOS\text{CMOS}CMOS

  4. RTL\text{RTL}RTL

Show me the answer

Answer: 3. CMOS\text{CMOS}CMOS

Explanation:

  • CMOS logic consumes the least power among the given options.

327. The complement of a variable is always:

  1. 000

  2. Equal to the variable\text{Equal to the variable}Equal to the variable

  3. 111

  4. The inverse of the variable\text{The inverse of the variable}The inverse of the variable

Show me the answer

Answer: 4. The inverse of the variable\text{The inverse of the variable}The inverse of the variable

Explanation:

  • The complement of a variable is its inverse (e.g., A‾\overline{A}A).

328. The Boolean expression A+B+CA + B + CA+B+C is:

  1. A sum term\text{A sum term}A sum term

  2. A product term\text{A product term}A product term

  3. A literal term\text{A literal term}A literal term

  4. A complement term\text{A complement term}A complement term

Show me the answer

Answer: 1. A sum term\text{A sum term}A sum term

Explanation:

  • The expression A+B+CA + B + CA+B+C is a sum term because it represents the logical OR of the variables.

329. The Boolean expression AB′CD′AB'CD'AB′CD′ is:

  1. A sum term\text{A sum term}A sum term

  2. A literal\text{A literal}A literal

  3. A product term\text{A product term}A product term

  4. Always 1\text{Always 1}Always 1

Show me the answer

Answer: 3. A product term\text{A product term}A product term

Explanation:

  • The expression AB′CD′AB'CD'AB′CD′ is a product term because it represents the logical AND of the variables.

330. The domain of the expression AB′CD+AB′+C′D+BAB'CD + AB' + C'D + BAB′CD+AB′+C′D+B is:

  1. A and DA \text{ and } DA and D

  2. A,B,C, and DA, B, C, \text{ and } DA,B,C, and D

  3. B onlyB \text{ only}B only

  4. None of the above\text{None of the above}None of the above

Show me the answer

Answer: 2. A,B,C, and DA, B, C, \text{ and } DA,B,C, and D

Explanation:

  • The domain of the expression includes all variables A,B,C, and DA, B, C, \text{ and } DA,B,C, and D.

331. According to the commutative law of addition:

  1. AB=BAAB = BAAB=BA

  2. A+(B+C)=(A+B)+CA + (B + C) = (A + B) + CA+(B+C)=(A+B)+C

  3. A=A+AA = A + AA=A+A

  4. A+B=B+AA + B = B + AA+B=B+A

Show me the answer

Answer: 4. A+B=B+AA + B = B + AA+B=B+A

Explanation:

  • The commutative law of addition states that the order of operands does not affect the result, so A+B=B+AA + B = B + AA+B=B+A.

332. According to the associative law of multiplication:

  1. B=BBB = BBB=BB

  2. A+B=B+AA + B = B + AA+B=B+A

  3. A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

  4. B+B(B+0)B + B(B + 0)B+B(B+0)

Show me the answer

Answer: 3. A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

Explanation:

  • The associative law of multiplication states that the grouping of operands does not affect the result, so A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C.

333. According to the distributive law:

  1. A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC

  2. A(A+1)=AA(A + 1) = AA(A+1)=A

  3. A(BC)=(AB)CA(BC) = (AB)CA(BC)=(AB)C

  4. A+AB=AA + AB = AA+AB=A

Show me the answer

Answer: 1. A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC

Explanation:

  • The distributive law states that multiplication distributes over addition, so A(B+C)=AB+ACA(B + C) = AB + ACA(B+C)=AB+AC.

334. Which one of the following is not a valid rule of Boolean algebra?

  1. A+1=1A + 1 = 1A+1=1

  2. AA=AAA = AAA=A

  3. A=AA = AA=A

  4. A+0=AA + 0 = AA+0=A

Show me the answer

Answer: 3. A=AA = AA=A

Explanation:

  • The statement A=AA = AA=A is not a rule of Boolean algebra; it is an identity.

335. Which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?

  1. A+1=1A + 1 = 1A+1=1

  2. AA=AAA = AAA=A

  3. A+A=AA + A = AA+A=A

  4. A⋅1=AA \cdot 1 = AA⋅1=A

Show me the answer

Answer: 4. A⋅1=AA \cdot 1 = AA⋅1=A

Explanation:

  • The rule A⋅1=AA \cdot 1 = AA⋅1=A states that if one input of an AND gate is 1, the output is equal to the other input.

336. According to De Morgan’s theorems, the following equality(s) are correct:

  1. AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}AB=A+B

  2. A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}A+B+C​=A⋅B⋅C

  3. XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}XYZ=X+Y+Z

  4. All of the above\text{All of the above}All of the above

Show me the answer

Answer: 4. All of the above\text{All of the above}All of the above

Explanation:

  • De Morgan’s theorems state that:

    • AB‾=A‾+B‾\overline{AB} = \overline{A} + \overline{B}AB=A+B

    • A+B+C‾=A‾⋅B‾⋅C‾\overline{A + B + C} = \overline{A} \cdot \overline{B} \cdot \overline{C}A+B+C​=A⋅B⋅C

    • XYZ‾=X‾+Y‾+Z‾\overline{XYZ} = \overline{X} + \overline{Y} + \overline{Z}XYZ=X+Y+Z

  • All the given equalities are correct.

337. The Boolean expression X=AB+CDX = AB + CDX=AB+CD represents:

  1. Two ORs ANDed together\text{Two ORs ANDed together}Two ORs ANDed together

  2. Two ANDs ORed together\text{Two ANDs ORed together}Two ANDs ORed together

  3. A 4-input AND gate\text{A 4-input AND gate}A 4-input AND gate

  4. An exclusive-OR\text{An exclusive-OR}An exclusive-OR

Show me the answer

Answer: 2. Two ANDs ORed together\text{Two ANDs ORed together}Two ANDs ORed together

Explanation:

  • The expression X=AB+CDX = AB + CDX=AB+CD represents two AND gates (ABABAB and CDCDCD) whose outputs are ORed together.

338. An example of a sum-of-products expression is:

  1. A+B(C+D)A + B(C + D)A+B(C+D)

  2. AB+AC+ABCAB + AC + ABCAB+AC+ABC

  3. (A+B+C)(A+B+C)(A + B + C)(A + B + C)(A+B+C)(A+B+C)

  4. Both answers A and B\text{Both answers A and B}Both answers A and B

Show me the answer

Answer: 2. AB+AC+ABCAB + AC + ABCAB+AC+ABC

Explanation:

  • A sum-of-products expression is a logical OR of multiple AND terms, such as AB+AC+ABCAB + AC + ABCAB+AC+ABC.

339. An example of a sum-of-sums expression is:

  1. A(B+C)+AGA(B + C) + AGA(B+C)+AG

  2. A+B+BCA + B + BCA+B+BC

  3. (A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C)

  4. Both answers A and B\text{Both answers A and B}Both answers A and B

Show me the answer

Answer: 3. (A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C)

Explanation:

  • A sum-of-sums expression is a logical AND of multiple OR terms, such as (A+B)(A+B+C)(A + B)(A + B + C)(A+B)(A+B+C).

340. An example of a standard SOP expression is:

  1. AB+ABC+ABDAB + ABC + ABDAB+ABC+ABD

  2. AB+AB+ABAB + AB + ABAB+AB+AB

  3. ABC+ACDABC + ACDABC+ACD

  4. ABCD+AB+AABCD + AB + AABCD+AB+A

Show me the answer

Answer: 3. ABC+ACDABC + ACDABC+ACD

Explanation:

  • A standard SOP (Sum of Products) expression consists of AND terms combined with OR, such as ABC+ACDABC + ACDABC+ACD.

341. A 3-variable Karnaugh map has:

  1. Eight cells\text{Eight cells}Eight cells

  2. Sixteen cells\text{Sixteen cells}Sixteen cells

  3. Three cells\text{Three cells}Three cells

  4. Four cells\text{Four cells}Four cells

Show me the answer

Answer: 1. Eight cells\text{Eight cells}Eight cells

Explanation:

  • A 3-variable Karnaugh map has 23=82^3 = 823=8 cells.

342. In a 4-variable Karnaugh map, a 2-variable product term is produced by:

  1. A 2-cell group of 1s\text{A 2-cell group of 1s}A 2-cell group of 1s

  2. A 4-cell group of 1s\text{A 4-cell group of 1s}A 4-cell group of 1s

  3. An 8-cell group of 1s\text{An 8-cell group of 1s}An 8-cell group of 1s

  4. A 4-cell group of 0s\text{A 4-cell group of 0s}A 4-cell group of 0s

Show me the answer

Answer: 2. A 4-cell group of 1s\text{A 4-cell group of 1s}A 4-cell group of 1s

Explanation:

  • A 2-variable product term is produced by a 4-cell group of 1s in a 4-variable Karnaugh map.

343. On a Karnaugh map, grouping the 0s produces:

  1. A product-of-sums expression\text{A product-of-sums expression}A product-of-sums expression

  2. A "don’t care" condition\text{A "don’t care" condition}A "don’t care" condition

  3. A sum-of-products expression\text{A sum-of-products expression}A sum-of-products expression

  4. AND-OR logic\text{AND-OR logic}AND-OR logic

Show me the answer

Answer: 1. A product-of-sums expression\text{A product-of-sums expression}A product-of-sums expression

Explanation:

  • Grouping 0s on a Karnaugh map produces a product-of-sums (POS) expression.

344. A 5-variable Karnaugh map has:

  1. Sixteen cells\text{Sixteen cells}Sixteen cells

  2. Sixty-four cells\text{Sixty-four cells}Sixty-four cells

  3. Thirty-two cells\text{Thirty-two cells}Thirty-two cells

  4. All of the above\text{All of the above}All of the above

Show me the answer

Answer: 3. Thirty-two cells\text{Thirty-two cells}Thirty-two cells

Explanation:

  • A 5-variable Karnaugh map has 25=322^5 = 3225=32 cells.

345. The output expression for an AND-OR circuit having one AND gate with inputs A,B,C,DA, B, C, DA,B,C,D and one AND gate with inputs E,FE, FE,F is:

  1. ABCDEFABCDEFABCDEF

  2. (A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

  3. AFE+C+D+E+FAFE + C + D + E + FAFE+C+D+E+F

  4. BCD+EFBCD + EFBCD+EF

Show me the answer

Answer: 4. BCD+EFBCD + EFBCD+EF

Explanation:

  • The output expression for the AND-OR circuit is BCD+EFBCD + EFBCD+EF.

346. A logic circuit with an output X=ABC+ACX = ABC + ACX=ABC+AC consists of:

  1. Two AND gates and one OR gate\text{Two AND gates and one OR gate}Two AND gates and one OR gate

  2. Two AND gates, one OR gate, and two inverters\text{Two AND gates, one OR gate, and two inverters}Two AND gates, one OR gate, and two inverters

  3. Two OR gates, one AND gate, and two inverters\text{Two OR gates, one AND gate, and two inverters}Two OR gates, one AND gate, and two inverters

  4. Two AND gates, one OR gate, and one inverter\text{Two AND gates, one OR gate, and one inverter}Two AND gates, one OR gate, and one inverter

Show me the answer

Answer: 1. Two AND gates and one OR gate\text{Two AND gates and one OR gate}Two AND gates and one OR gate

Explanation:

  • The expression X=ABC+ACX = ABC + ACX=ABC+AC requires two AND gates (for ABCABCABC and ACACAC) and one OR gate.

347. To implement the expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD, it takes one OR gate and:

  1. One AND gate\text{One AND gate}One AND gate

  2. Three AND gates and four inverters\text{Three AND gates and four inverters}Three AND gates and four inverters

  3. Three AND gates\text{Three AND gates}Three AND gates

  4. Three AND gates and three inverters\text{Three AND gates and three inverters}Three AND gates and three inverters

Show me the answer

Answer: 3. Three AND gates\text{Three AND gates}Three AND gates

Explanation:

  • The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD requires three AND gates and one OR gate.

348. The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD:

  1. Cannot be simplified\text{Cannot be simplified}Cannot be simplified

  2. Can be simplified to ABCD+ABC\text{Can be simplified to } ABCD + ABCCan be simplified to ABCD+ABC

  3. Can be simplified to ABC+AB\text{Can be simplified to } ABC + ABCan be simplified to ABC+AB

  4. None of these answers is correct\text{None of these answers is correct}None of these answers is correct

Show me the answer

Answer: 1. Cannot be simplified\text{Cannot be simplified}Cannot be simplified

Explanation:

  • The expression ABCD+ABCD+ABCDABCD + ABCD + ABCDABCD+ABCD+ABCD is already in its simplest form and cannot be further simplified.

349. The input expression for an AND-OR-Invert circuit having one AND gate with inputs A,B,C,DA, B, C, DA,B,C,D and one AND gate with inputs E,FE, FE,F is:

  1. ABCD+EFABCD + EFABCD+EF

  2. A+B+C+D+E+FA + B + C + D + E + FA+B+C+D+E+F

  3. (A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

  4. (A+B+C+D)(E+F)(A + B + C + D)(E + F)(A+B+C+D)(E+F)

Show me the answer

Answer: 1. ABCD+EFABCD + EFABCD+EF

Explanation:

  • The input expression for the AND-OR-Invert circuit is ABCD+EFABCD + EFABCD+EF.

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