set-3

101. What is the 2’s complement of 0011 0101 1001 1100?

  1. 11001001110010111100 1001 1100 1011

  2. 11001010011001001100 1010 0110 0100

  3. 11001010011000111100 1010 0110 0011

  4. 11001010111111111100 1010 1111 1111

Show me the answer

Answer: 3. 11001010011000111100 1010 0110 0011

Explanation:

  • To find the 2’s complement:

    1. Invert all bits: 11001010011000111100 1010 0110 0011

    2. Add 1 to the least significant bit (LSB): 1100101001100011+1=11001010011001001100 1010 0110 0011 + 1 = 1100 1010 0110 0100.

102. A flip-flop is a:

  1. Chip\text{Chip}

  2. I/O element\text{I/O element}

  3. Memory element\text{Memory element}

  4. Bus\text{Bus}

Show me the answer

Answer: 3. Memory element\text{Memory element}

Explanation:

  • A flip-flop is a basic memory element that stores one bit of data.

103. With an RS latch, a high S and low R sets the output to:

  1. No change\text{No change}

  2. High\text{High}

  3. Race\text{Race}

  4. Set\text{Set}

Show me the answer

Answer: 2. High\text{High}

Explanation:

  • In an RS latch, when S (Set) is high and R (Reset) is low, the output is set to high.

104. With a NAND latch, a low R and a low S produce a:

  1. Race condition\text{Race condition}

  2. Reset condition\text{Reset condition}

  3. Set condition\text{Set condition}

  4. No change condition\text{No change condition}

Show me the answer

Answer: 1. Race condition\text{Race condition}

Explanation:

  • In a NAND latch, when both R and S are low, it creates a race condition, which is an invalid state.

105. Computers use thousands of flip-flops. To coordinate the overall action, a common signal called the:

  1. Latch\text{Latch}

  2. Master\text{Master}

  3. Clock\text{Clock}

  4. Slave\text{Slave}

Show me the answer

Answer: 3. Clock\text{Clock}

Explanation:

  • The clock signal synchronizes the operation of flip-flops and other components in a computer.

106. With positive clocking, the clock signal must be:

  1. High\text{High}

  2. Set\text{Set}

  3. Low\text{Low}

  4. Race\text{Race}

Show me the answer

Answer: 1. High\text{High}

Explanation:

  • In positive clocking, the flip-flop responds when the clock signal is high.

107. With a JK master-slave flip-flop, the master is clocked when the clock is:

  1. Set, reset\text{Set, reset}

  2. High, low\text{High, low}

  3. Race, no change\text{Race, no change}

  4. Set, race\text{Set, race}

Show me the answer

Answer: 2. High, low\text{High, low}

Explanation:

  • In a JK master-slave flip-flop, the master is clocked when the clock is high, and the slave is triggered when the clock is low.

108. When the LOAD input of a buffer register is active, the input word is stored on the next positive:

  1. Clock edge\text{Clock edge}

  2. Register\text{Register}

  3. Pulse\text{Pulse}

  4. Transistor\text{Transistor}

Show me the answer

Answer: 1. Clock edge\text{Clock edge}

Explanation:

  • The input word is stored in the buffer register on the next positive clock edge when the LOAD input is active.

109. A shift register moves the bits:

  1. Left or right\text{Left or right}

  2. Up or down\text{Up or down}

  3. Forward or backward\text{Forward or backward}

  4. None of the above\text{None of the above}

Show me the answer

Answer: 1. Left or right\text{Left or right}

Explanation:

  • A shift register shifts bits either to the left or to the right.

110. One flip-flop divides the clock frequency by a factor of:

  1. Two\text{Two}

  2. Four\text{Four}

  3. Eight\text{Eight}

  4. Sixteen\text{Sixteen}

Show me the answer

Answer: 1. Two\text{Two}

Explanation:

  • A single flip-flop divides the clock frequency by 2.

111. Instead of counting with binary numbers, a ring counter uses words that have a single high:

  1. Byte\text{Byte}

  2. Gate\text{Gate}

  3. Bit\text{Bit}

  4. Chip\text{Chip}

Show me the answer

Answer: 3. Bit\text{Bit}

Explanation:

  • A ring counter uses words with a single high bit that circulates through the register.

112. The memory that is ultraviolet-light erasable and electrically programmable is:

  1. EPROM\text{EPROM}

  2. PROM\text{PROM}

  3. ROM\text{ROM}

  4. RAM\text{RAM}

Show me the answer

Answer: 1. EPROM\text{EPROM}

Explanation:

  • EPROM (Erasable Programmable Read-Only Memory) can be erased using ultraviolet light and reprogrammed electrically.

113. The memory cell of a dynamic RAM is simpler and smaller than the memory cell of a:

  1. Volatile RAM\text{Volatile RAM}

  2. Semiconductor RAM\text{Semiconductor RAM}

  3. Static RAM\text{Static RAM}

  4. Bipolar RAM\text{Bipolar RAM}

Show me the answer

Answer: 3. Static RAM\text{Static RAM}

Explanation:

  • Dynamic RAM (DRAM) uses a simpler and smaller memory cell compared to Static RAM (SRAM).

114. How many memory locations can 14 address bits access?

  1. 16,38416,384

  2. 4,0964,096

  3. 8,1928,192

  4. 1414

Show me the answer

Answer: 1. 16,38416,384

Explanation:

  • With 14 address bits, the number of memory locations is 214=16,3842^{14} = 16,384.

115. The 2764 is a 65,536-bit EPROM organized as 8,192 words of 8 bits each. How many address lines does it have?

  1. 1212

  2. 1313

  3. 1414

  4. 88

Show me the answer

Answer: 2. 1313

Explanation:

  • To address 8,192 words, the number of address lines required is log⁡28192=13\log_2{8192} = 13.

116. The 2732 is a 4096x8 EPROM. How many address lines does it have?

  1. 1212

  2. 1313

  3. 1414

  4. 88

Show me the answer

Answer: 1. 1212

Explanation:

  • To address 4,096 words, the number of address lines required is log⁡24096=12\log_2{4096} = 12.

117. Address 200H contains the byte 3FH. What is the decimal equivalent of 3FH?

  1. 6363

  2. 1616

  3. 2222

  4. 3838

Show me the answer

Answer: 1. 6363

Explanation:

  • The hexadecimal value 3FH is equivalent to 3×16+15=633 \times 16 + 15 = 63 in decimal.

118. What is the highest address in a 48K memory? Express in hexadecimal and decimal form.

  1. 7FFFH,643877FFFH, 64387

  2. BFFFH,49,152BFFFH, 49,152

  3. BFFFH,49,151BFFFH, 49,151

  4. 7FFFH,64,3867FFFH, 64,386

Show me the answer

Answer: 3. BFFFH,49,151BFFFH, 49,151

Explanation:

  • 48K memory corresponds to 48×1024=49,15248 \times 1024 = 49,152 bytes.

  • The highest address is 49,152−1=49,15149,152 - 1 = 49,151, which is BFFFH in hexadecimal.

119. Flip-flop outputs are always:

  1. Complimentary\text{Complimentary}

  2. Independent of each other\text{Independent of each other}

  3. The same\text{The same}

  4. Same as inputs\text{Same as inputs}

Show me the answer

Answer: 1. Complimentary\text{Complimentary}

Explanation:

  • The outputs of a flip-flop (Q and Q') are always complementary.

120. A combinational logic circuit used to send data from a single source to two or more separate destinations is called:

  1. Decoder\text{Decoder}

  2. Multiplexer\text{Multiplexer}

  3. Encoder\text{Encoder}

  4. Demultiplexer\text{Demultiplexer}

Show me the answer

Answer: 4. Demultiplexer\text{Demultiplexer}

Explanation:

  • A demultiplexer sends data from one input to one of several outputs based on the control signals.

121. In which of the following adder circuits is the carry look ripple delay eliminated?

  1. Half adder\text{Half adder}

  2. Parallel adder\text{Parallel adder}

  3. Full adder\text{Full adder}

  4. Carry-look-ahead adder\text{Carry-look-ahead adder}

Show me the answer

Answer: 4. Carry-look-ahead adder\text{Carry-look-ahead adder}

Explanation:

  • The carry-look-ahead adder eliminates the ripple delay by calculating carry signals in advance.

122. Consider an RS flip-flop with both inputs set to 0. If a momentary '1' is applied at the input S, then the output:

  1. Q will flip from 0 to 1Q \text{ will flip from 0 to 1}

  2. Q will flip from 0 to 1 and then back to 0Q \text{ will flip from 0 to 1 and then back to 0}

  3. Q will remain unchangedQ \text{ will remain unchanged}

  4. Q will flip from 1 to 0Q \text{ will flip from 1 to 0}

Show me the answer

Answer: 1. Q will flip from 0 to 1Q \text{ will flip from 0 to 1}

Explanation:

  • In an RS flip-flop, applying a momentary '1' to the S (Set) input will set the output Q to 1.

123. How many full adders are required to construct an m-bit parallel adder?

  1. m/2m/2

  2. m−1m-1

  3. mm

  4. m+1m+1

Show me the answer

Answer: 3. mm

Explanation:

  • An m-bit parallel adder requires m full adders, one for each bit.

124. The dynamic race hazard problem occurs in:

  1. Combinational circuits only\text{Combinational circuits only}

  2. Sequential circuits only\text{Sequential circuits only}

  3. Both combinational and sequential circuits\text{Both combinational and sequential circuits}

  4. None of the above\text{None of the above}

Show me the answer

Answer: 2. Sequential circuits only\text{Sequential circuits only}

Explanation:

  • The dynamic race hazard problem occurs in sequential circuits due to timing issues in signal propagation.

125. A shift register can be used for:

  1. Parallel to serial conversion\text{Parallel to serial conversion}

  2. Digital delay line\text{Digital delay line}

  3. Serial to parallel conversion\text{Serial to parallel conversion}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 4. All of the above\text{All of the above}

Explanation:

  • A shift register can perform parallel-to-serial conversion, serial-to-parallel conversion, and act as a digital delay line.

126. Which of the following flip-flops is free from the race-around problem?

  1. T flip-flop\text{T flip-flop}

  2. Master-slave JK flip-flop\text{Master-slave JK flip-flop}

  3. SR flip-flop\text{SR flip-flop}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 2. Master-slave JK flip-flop\text{Master-slave JK flip-flop}

Explanation:

  • The master-slave JK flip-flop is designed to eliminate the race-around problem.

127. For an input pulse train of clock period T, the delay produced by an n-stage shift register is:

  1. (n+1)T(n+1)T

  2. (n−1)T(n-1)T

  3. nTnT

  4. 2nT2nT

Show me the answer

Answer: 3. nTnT

Explanation:

  • An n-stage shift register introduces a delay of n clock periods (nT).

128. The master-slave JK flip-flop is effectively a combination of:

  1. An SR flip-flop and a T flip-flop\text{An SR flip-flop and a T flip-flop}

  2. An SR flip-flop and a D flip-flop\text{An SR flip-flop and a D flip-flop}

  3. A T flip-flop and a D flip-flop\text{A T flip-flop and a D flip-flop}

  4. Two T flip-flops\text{Two T flip-flops}

Show me the answer

Answer: 1. An SR flip-flop and a T flip-flop\text{An SR flip-flop and a T flip-flop}

Explanation:

  • The master-slave JK flip-flop combines the functionality of an SR flip-flop and a T flip-flop.

129. The functional difference between SR flip-flop and JK flip-flop is:

  1. JK flip-flop is faster than SR flip-flop\text{JK flip-flop is faster than SR flip-flop}

  2. JK flip-flop has a feedback path\text{JK flip-flop has a feedback path}

  3. JK flip-flop accepts both input 1\text{JK flip-flop accepts both input 1}

  4. JK flip-flop does not require an external clock\text{JK flip-flop does not require an external clock}

Show me the answer

Answer: 2. JK flip-flop has a feedback path\text{JK flip-flop has a feedback path}

Explanation:

  • The JK flip-flop has a feedback path that allows it to toggle its output when both inputs are high.

130. The term sum-of-products in Boolean algebra means:

  1. The AND function of several OR functions\text{The AND function of several OR functions}

  2. The OR function of several AND functions\text{The OR function of several AND functions}

  3. The OR function of several OR functions\text{The OR function of several OR functions}

  4. The AND function of several AND functions\text{The AND function of several AND functions}

Show me the answer

Answer: 2. The OR function of several AND functions\text{The OR function of several AND functions}

Explanation:

  • Sum-of-products (SOP) refers to the OR of multiple AND terms.

131. A positive AND gate is also a negative:

  1. NAND gate\text{NAND gate}

  2. AND gate\text{AND gate}

  3. NOR gate\text{NOR gate}

  4. OR gate\text{OR gate}

Show me the answer

Answer: 3. NOR gate\text{NOR gate}

Explanation:

  • A positive AND gate behaves like a negative NOR gate due to De Morgan's laws.

132. What table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs?

  1. Function table\text{Function table}

  2. Routing table\text{Routing table}

  3. Truth table\text{Truth table}

  4. ASCII table\text{ASCII table}

Show me the answer

Answer: 3. Truth table\text{Truth table}

Explanation:

  • A truth table shows the output of a digital circuit for all possible input combinations.

133. How many bits are required to encode all twenty-six letters, ten symbols, and ten numbers?

  1. 55

  2. 22

  3. 66

  4. 33

Show me the answer

Answer: 3. 66

Explanation:

  • To encode 26 letters, 10 symbols, and 10 numbers (total 46 items), at least 6 bits are required (26=642^6 = 64).

134. The number of two-input NAND gates required to produce the two-input OR function is:

  1. 11

  2. 33

  3. 22

  4. 44

Show me the answer

Answer: 2. 33

Explanation:

  • To implement a two-input OR function using NAND gates, three NAND gates are required.

135. What logic function is obtained by adding an inverter to the inputs of an AND gate?

  1. OR\text{OR}

  2. XOR\text{XOR}

  3. NAND\text{NAND}

  4. NOR\text{NOR}

Show me the answer

Answer: 4. NOR\text{NOR}

Explanation:

  • Adding inverters to the inputs of an AND gate results in a NOR gate.

136. Which of the following Boolean algebra expressions is incorrect?

  1. AB+A(B+C)+B(B+C)=B+ACAB + A(B + C) + B(B + C) = B + AC

  2. [AB(C+BD)+AB]C=BC[AB(C + BD) + AB]C = BC

  3. AB(C+D)=A+B+CDAB(C + D) = A + B + CD

  4. (A+C)(ABC+ACD)=ABC+ACD(A + C)(ABC + ACD) = ABC + ACD

Show me the answer

Answer: 3. AB(C+D)=A+B+CDAB(C + D) = A + B + CD

Explanation:

  • The expression AB(C+D)AB(C + D) simplifies to ABC+ABDABC + ABD, not A+B+CDA + B + CD.

137. Which gate is known as the universal gate?

  1. NOT gate\text{NOT gate}

  2. NAND gate\text{NAND gate}

  3. AND gate\text{AND gate}

  4. XOR gate\text{XOR gate}

Show me the answer

Answer: 2. NAND gate\text{NAND gate}

Explanation:

  • The NAND gate is a universal gate because it can be used to implement any other logic gate.

138. What logic function is produced by adding an inverter to the output of an AND gate?

  1. NAND\text{NAND}

  2. XOR\text{XOR}

  3. NOR\text{NOR}

  4. OR\text{OR}

Show me the answer

Answer: 1. NAND\text{NAND}

Explanation:

  • Adding an inverter to the output of an AND gate produces a NAND gate.

139. An OR gate can be imagined as:

  1. Switches connected in parallel\text{Switches connected in parallel}

  2. MOS transistors connected in series\text{MOS transistors connected in series}

  3. Switches connected in series\text{Switches connected in series}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 1. Switches connected in parallel\text{Switches connected in parallel}

Explanation:

  • An OR gate behaves like switches connected in parallel, where the output is high if any input is high.

140. What logic function is produced by adding an inverter to each input and the output of an AND gate?

  1. NAND\text{NAND}

  2. OR\text{OR}

  3. NOR\text{NOR}

  4. XOR\text{XOR}

Show me the answer

Answer: 3. NOR\text{NOR}

Explanation:

  • Adding inverters to the inputs and output of an AND gate produces a NOR gate.

141. Which of the following algebra statements represents the commutative law?

  1. (A+B)+C=A+(B+C)(A + B) + C = A + (B + C)

  2. A+B=B+AA + B = B + A

  3. A⋅(B+C)=(A⋅B)+(A⋅C)A \cdot (B + C) = (A \cdot B) + (A \cdot C)

  4. A+A=AA + A = A

Show me the answer

Answer: 2. A+B=B+AA + B = B + A

Explanation:

  • The commutative law states that the order of operands does not affect the result in addition or multiplication.

142. For what logic gate is the output the complement of the input?

  1. NOT\text{NOT}

  2. OR\text{OR}

  3. AND\text{AND}

  4. XOR\text{XOR}

Show me the answer

Answer: 1. NOT\text{NOT}

Explanation:

  • The NOT gate outputs the complement of the input.

143. ASCII and EBCDIC differ in:

  1. Their efficiency in storing data\text{Their efficiency in storing data}

  2. The random and sequential access method\text{The random and sequential access method}

  3. The number of bytes used to store characters\text{The number of bytes used to store characters}

  4. Their encoding sequences\text{Their encoding sequences}

Show me the answer

Answer: 4. Their encoding sequences\text{Their encoding sequences}

Explanation:

  • ASCII and EBCDIC use different encoding sequences to represent characters.

144. In which code do successive code characters differ in only one bit position?

  1. Gray code\text{Gray code}

  2. 8421 code\text{8421 code}

  3. Excess-3 code\text{Excess-3 code}

  4. Algebraic code\text{Algebraic code}

Show me the answer

Answer: 1. Gray code\text{Gray code}

Explanation:

  • Gray code ensures that successive values differ by only one bit.

145. Cyclic codes are used in:

  1. Data transfer\text{Data transfer}

  2. Continuously varying signals\text{Continuously varying signals}

  3. Arithmetic and logical computation\text{Arithmetic and logical computation}

  4. All of the above\text{All of the above}

Show me the answer

Answer: 4. All of the above\text{All of the above}

Explanation:

  • Cyclic codes are used in data transfer, signal processing, and computation.

146. The 2's complement of the binary number 010111.1100 is:

  1. 101001.1100101001.1100

  2. 010111.0011010111.0011

  3. 101000.0100101000.0100

  4. 101000.0011101000.0011

Show me the answer

Answer: 3. 101000.0100101000.0100

Explanation:

  • To find the 2's complement:

    1. Invert all bits: 101000.0011101000.0011

    2. Add 1 to the least significant bit (LSB): 101000.0100101000.0100.

147. The ASCII code:

  1. Is a subset of 8-bit EBCDIC\text{Is a subset of 8-bit EBCDIC}

  2. Is used only in Western countries\text{Is used only in Western countries}

  3. Is version II of the ASC standard\text{Is version II of the ASC standard}

  4. Has 128 characters, including 32 control characters\text{Has 128 characters, including 32 control characters}

Show me the answer

Answer: 4. Has 128 characters, including 32 control characters\text{Has 128 characters, including 32 control characters}

Explanation:

  • The ASCII code includes 128 characters, with 32 being control characters.

148. The Gray code for decimal 7 is:

  1. 01110111

  2. 01000100

  3. 10111011

  4. 10101010

Show me the answer

Answer: 2. 01000100

Explanation:

  • The Gray code for decimal 7 is 0100.

149. The octal equivalent of decimal 324.987 is:

  1. 504.771504.771

  2. 815.234815.234

  3. 640.781640.781

  4. 90.98790.987

Show me the answer

Answer: 1. 504.771504.771

Explanation:

  • The octal equivalent of decimal 324.987 is 504.771.

150. When an odd number is converted into a binary number, the least significant digit (LSD) is:

  1. 00

  2. 0 or 10 \text{ or } 1

  3. 11

  4. All of the above\text{All of the above}

Show me the answer

Answer: 3. 11

Explanation:

  • The least significant digit (LSD) of an odd binary number is always 1.

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