4.1 Control and CPU

In this section, we focus on the control unit of a computer system, the structure of the CPU, its components, and the different instruction formats and addressing modes. We will also cover RISC and CISC architectures, and how pipelining is used to improve CPU performance.

1. Control Memory and Addressing Sequencing

  • Control Memory: Control memory is used to store control information in the form of micro-operations. It determines how the CPU handles instruction execution. The control unit uses control memory to fetch, decode, and execute instructions.

  • Addressing Sequencing: Addressing sequencing refers to the order and method in which addresses are generated during the fetch and execution of instructions. The sequence of addresses helps the control unit fetch the appropriate data from memory or registers.

  • Computer Configuration: The computer configuration involves the organization of various components such as the CPU, memory, and input/output devices. The configuration ensures that all components work together efficiently.

2. CPU Structure

The CPU (Central Processing Unit) is the brain of the computer. It executes instructions and coordinates the activities of other hardware components. The CPU consists of several key components:

  • Control Unit (CU): The control unit coordinates the activities of the CPU by interpreting and executing instructions. It sends control signals to other components and manages data flow.

  • Arithmetic Logic Unit (ALU): The ALU performs arithmetic and logical operations, such as addition, subtraction, multiplication, division, and logical operations like AND, OR, NOT.

  • Registers: Registers are small, fast storage locations within the CPU used to store temporary data, such as operands and results during computation.

  • Instruction Register (IR): The instruction register holds the instruction that is currently being executed. It stores the binary representation of the instruction fetched from memory.

  • Program Counter (PC): The program counter holds the address of the next instruction to be executed. It is updated after each instruction to point to the subsequent instruction.

3. Instruction Formats

An instruction is a binary code that represents a command for the CPU to execute. Instructions are typically divided into different fields:

  • Opcode (Operation Code): Specifies the operation to be performed (e.g., addition, subtraction, etc.).

  • Operand(s): The data on which the operation is performed (e.g., a value or address).

  • Addressing Mode: Specifies how the operands are accessed (e.g., immediate, direct, indirect).

Example of an Instruction Format:

An instruction might be formatted as follows:

| Opcode | Operand 1 | Operand 2 | Addressing Mode |

Where:

  • Opcode specifies the operation to be performed.

  • Operands represent the values or addresses involved.

  • Addressing mode indicates how to interpret the operands.

4. Addressing Modes

Addressing modes determine how operands are fetched for an instruction. There are several types of addressing modes:

  • Immediate Addressing: The operand is a constant value embedded within the instruction.

    • Example: MOV A, #5 (Move the immediate value 5 into register A)

  • Direct Addressing: The operand is a memory address directly specified in the instruction.

    • Example: MOV A, 2000 (Move the value of memory address 2000 into register A)

  • Indirect Addressing: The instruction provides a memory address that points to the operand.

    • Example: MOV A, [R1] (Move the value the of memory address stored in register R1 into register A)

  • Register Addressing: The operand is stored in a register, and the instruction specifies the register.

    • Example: MOV A, R1 (Move the value of register R1 into register A)

5. RISC vs CISC

  • RISC (Reduced Instruction Set Computing):

    • RISC focuses on a small set of simple instructions that are highly optimized for fast execution. Each instruction is designed to execute in a single clock cycle, improving efficiency and performance.

  • CISC (Complex Instruction Set Computing):

    • CISC aims to provide a wide range of complex instructions that can perform multiple tasks in a single operation. These instructions are designed to minimize the number of instructions per program, even if each instruction takes multiple cycles to execute.

Key Differences Between RISC and CISC

Feature
RISC
CISC

Instruction Set

Small, simple, fixed-size

Large, complex, variable-size

Execution Time

One clock cycle per instruction

Multiple cycles per instruction

Registers

More registers

Fewer registers

Memory Access

Load/store architecture

Memory access within instructions

Hardware Design

Simple, efficient

Complex, costly

Program Size

Larger

Smaller

Pipelining

Easy to implement

Difficult to implement

Examples

ARM, MIPS, PowerPC

x86, Intel, AMD

Real-World Usage:

  • RISC: Preferred for energy-efficient and performance-critical systems like smartphones, embedded devices, and IoT.

  • CISC: Dominates desktop and laptop processors due to backward compatibility and optimized performance for complex applications.

Both architectures have their strengths and are often hybridized in modern processors. For example, modern x86 processors use a combination of RISC-like and CISC-like features.

6. Pipelining in CPU

Pipelining is a technique used to improve the performance of a CPU by overlapping the stages of instruction execution. In pipelining, an instruction is divided into stages, and multiple instructions are processed simultaneously, with each stage handling a different instruction.

  • Stages of Instruction Pipeline:

    • Fetch: The instruction is fetched from memory.

    • Decode: The instruction is decoded to determine the operation and operands.

    • Execute: The operation is performed (e.g., ALU operations).

    • Memory Access: If the instruction involves memory access, this stage handles it.

    • Write Back: The result is written back to the register.

  • Pipeline Hazards: Pipelining can encounter hazards, which are situations where instructions cannot proceed as planned. These include:

    1. Data Hazard

    • Definition: A data hazard occurs when an instruction depends on the data result of a previous instruction that has not yet completed in the pipeline.

    • Example:

      • Instruction 1: ADD R1, R2, R3 (Result stored in R1)

      • Instruction 2: SUB R4, R1, R5 (Needs R1 from Instruction 1)

      • If Instruction 2 executes before Instruction 1 writes its result to R1, a data hazard occurs.

    • Types:

      • Read After Write (RAW): A subsequent instruction reads a value that a previous instruction writes.

      • Write After Write (WAW): Two instructions write to the same location in an order that conflicts.

      • Write After Read (WAR): A subsequent instruction writes to a location before a previous instruction reads it.

    2. Control Hazard

    • Definition: A control hazard occurs when the pipeline's control flow changes, typically due to branch instructions (if, else, loops) or jumps.

    • Example:

      • Here's a very simple 8085 example:

        CMP B        ; Compare A with B
JZ LABEL     ; If A == B, jump to LAB

      • CMP B: Compares the contents of register A with register B and sets the Zero flag if they are equal.

      • JZ LABEL:

        • If the Zero flag is set (A == B), the program jumps to the address labeled LABEL.

        • Otherwise, it continues executing the next instruction in sequence.

    • Control Hazard (If Pipelining Existed):

      • While the CMP B instruction is being executed, the pipeline does not know if the branch (JZ LABEL) will be taken.

      • It might fetch the next instruction sequentially.

        • If the branch is taken, the pipeline has to discard the fetched instruction and fetch the one at LABEL, causing a stall.

    • Impact: The pipeline may fetch incorrect instructions until the branch decision is resolved.

    • Solution:

      • Stalling: Stop fetching new instructions until the branch decision is resolved.

      • Branch Prediction: Guess whether the branch will be taken or not; flush the pipeline if the guess is wrong.

      • Delayed Branch: Place independent instructions after the branch to execute during the decision delay.

3. Structural Hazard

  • Definition: A structural hazard occurs when the pipeline's hardware resources (e.g., memory, ALUs) are insufficient to handle multiple instructions simultaneously.

  • Example:

    • If a pipeline has only one memory unit and multiple instructions simultaneously require memory access, a structural hazard arises.

  • Impact: Leads to delays as instructions must wait for resources to become available.

  • Solution:

    • Hardware Duplication: Add more functional units.

    • Instruction Scheduling: Rearrange instructions to avoid contention.

  • Example of Pipelining: Suppose we have a series of instructions that can be executed in a pipeline:

    Instruction 1: Fetch → Decode → Execute → Memory → Write Back
Instruction 2:         Fetch → Decode → Execute → Memory → Write Back
Instruction 3:               Fetch → Decode → Execute → Memory → Write Back

In this way, while one instruction is being executed, the next instruction can be decoded, and the one after that can be fetched, improving overall performance.

Conclusion

  • Control Memory and Addressing Sequencing: Control memory stores instructions that direct the CPU. Addressing sequencing manages the order of fetching addresses for instruction execution.

  • CPU Structure: The CPU consists of the control unit, ALU, registers, and various other components for executing instructions.

  • Instruction Formats and Addressing Modes: Instructions consist of opcodes and operands. The addressing mode specifies how operands are accessed.

  • RISC vs CISC: RISC uses a small set of simple instructions, while CISC uses more complex instructions. RISC processors tend to be faster due to simpler instructions.

  • Pipelining: Pipelining improves CPU performance by allowing multiple instructions to be processed at different stages simultaneously.

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