set-7
301. A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this pointer?
Pointers
Records
Arrays
All of the above
302. The 8085 microprocessor responds to the presence of an interrupt:
As soon as the TRAP pin becomes high
By checking the TRAP pin for high status at the end of each instruction fetch
By checking the TRAP pin for high status at the end of the execution of each instruction
By checking the TRAP pin for high status at regular intervals
303. Which of the following need not necessarily be saved on a context switch between processes?
General purpose registers
Program counter
Translation look aside buffer
All of these
304. If a processor does not have any stack pointer register then:
It cannot have subroutine call instruction
It can have subroutine call instruction, but no nested subroutine calls
Nested subroutine calls are possible, but interrupts are not
All sequence of subroutine calls and also interrupts are possible
305. CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged:
A hardware interrupt is needed
A software interrupt is needed
A privileged instruction (which does not generate an interrupt) is needed
A non-privileged instruction (which does not generate an interrupt) is needed
306. In the absolute addressing mode:
An operand is inside the instruction
Address of the operand is inside the instruction
Register containing the address of the operand is specified inside the instruction
Location of the operand is implicit
307. The capacity of program counter (PC) is:
8 bits
16 bits
12 bits
32 bits
308. The function of program counter (PC) holds:
Temporary
Memory operand
Address for memory
Address for instruction
309. The Program Counter (PC):
Is a register
During execution of the current instruction, its content changes
Both (A) and (B)
None of the above
310. The TRAP interrupt mechanism of the 8085 microprocessor executes:
An RST by hardware
The instructions supplied by external device through the INTA signal
An instruction from memory location 20H
None of the above
311. Pseudo-instructions are:
Assembler directives
Instructions in any program that have no corresponding machine code instruction
Instruction in any program whose presence or absence will not change the output for any input
None of the above
312. “The number of instructions needed to add ‘n’ numbers and store the result in memory using only one address instructions is:
n
n-1
n+1
Independent of n
313. The addressing mode used in the instruction PUSH B is:
Direct
Register indirect
Register
Immediate
314. The process of fetching and executing instructions one at a time, in order to increasing an address is called:
Instruction execution
Instruction fetch
Straight line sequencing
Random sequencing
315. The CPU of a computer takes instruction from the memory and executes them. This process is called:
Load cycle
Fetch-execute cycle
Time sequence
Clock cycle
316. In a microprocessor, WAIT states are used to:
Make the processor wait during a DMA operation
Make the processor wait during a power interrupt processing
Make the processor wait during a power shutdown
Interface slow peripheral to the processor
317. When a program is being executed in an 8085 microprocessor, its program counter contains:
Number of instructions in the current program that have already been executed
The total number of instructions in the program being executed
Memory address of the instructions that is being currently executed
Memory address of the instructions that is to be executed next
318. When the HLT instructions of an 8085 microprocessor is executed, the microprocessor:
Is disconnected from the system bus till the reset is pressed
Halts execution of the program and returns to monitor
Enters into a halt-state and the buses are tri-stated
Reloads the program from the location 0024 and 0025
319. Serial input data of 8085 can be loaded into bit 7 of the accumulator by:
Executing a RIM instruction
Using TRAP
Executing RST 1
None of the above
320. Which of the following interrupts are unmaskable interrupts?
RST 5.5
TRAP
RST 7.5
INTR 1
321. The memory address ranges to which RAM will respond:
0000 H to 1 FFF H
4000 H to 5 FFF H
0000 H to 5 FFF H
3000 H to FFFF H
322. The address range to which I/O chip will respond is:
0000 H to FFFF H
4000H to 5FFF H
0000H to 5FFFH
3000 H to FFFF H
323. Both the arithmetic logic unit (ALU) and control section of CPU employ special purpose storage location called:
Decoder
Multiplexer
Buffers
Registers
324. A basic instruction that can be interpreted by a computer generally has:
An operand and an address
Sequence register and decoder
A decoder and an accumulator
An address and decoder
325. The differences between PLA and ROM is:
PLA is combination ROM is sequential
PLA economizes on the number of minterms
PLA has fixed AND array, ROM has fixed OR array
None of these
326. The control unit of computer:
Performs ALU operations on the data
Controls the operation of the output devices
Is a device for manually operating the computer
Directs the other unit of computers
327. The ALU of a computer normally contains a number of high-speed storage elements called:
Semiconductor memory
Hard disk
Registers
Magnetic disks
328. The unit of a computer system which executes program, communication with and often controls the operation of other subsystems of the computer is the:
CPU
I/O unit
Control unit
Peripheral unit
329. The ability of a medium size computer system to increase in data processing capability by addition of such devices as mass storage device, I/O device etc. is called:
Computer expandability
Computer enhancement
Computer mobility
Computer upward capability
330. The technique which repeatedly uses the same block of internal storage during different stage of problem is called:
Overlay
Swapping
Overlapping
Reuse
331. The registers used as a working area in CPU is:
Program counter
Instruction decoder
Instruction register
Accumulator
332. Which of the following information holds the information before going to the decoder?
Control register
Accumulator
Data register
Address register
333. Which of the following unit is used to supervise each instruction in the CPU?
Control logic unit
ALU
Accumulator
Control register
334. The bus which is used to transfer data from main memory to peripheral device is:
Data bus
DMA bus
Input bus
Output bus
335. The device which is used to connect a peripheral to bus is called:
Control register
Communication protocol
Interface
None of these
336. The bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is called:
DMA bus
Address bus
Memory bus
Control bus
337. What is the storage capacity of a Hollerith card which is organized into nibbles?
32
120
64
240
338. How many addresses are required for 25x40 video RAM?
1020
1000
1920
2000
339. Microprogramming is a technique for:
Writing small program effectively
Programming output/input routines
Programming the microprocessor
Programming the control steps of a computer
340. A device that works in conjunction with a computer but not as part of it is called:
Microprocessor
Hardware
Peripheral device
Memory
341. A system of letters, numbers symbols adopted by computer manufacture as an abbreviation form of instruction sets is called
Mesh
Modern
Monitor
Mnemonic
342. When a subroutine is called, then address of the instruction following the CALL instruction is stored in/on the
Stack pointer
Program counter
Accumulator
Stack
343. In 8085 microprocessors, the value of the most significant bit of the result following the execution of any arithmetic or Boolean instruction is stored in the
Carry status flag
Sign status flag
Auxiliary carry status flag
Zero status flag
344. PLA
Produces sum of products as the outputs
Is dedicated for a particular operation
Is general
Both A and B
345. The sequence of events that happen during a typical fetch operation is
PC-MAR-Memory-MDR-IR
PC-Memory-IR
PC-Memory-MDR-IR
PC-MAR-Memory-IR
346. Which of the following is not a form of memory?
Instruction cache
Instruction opcode
Instruction register
Translation lookaside buffer
347. Which memory is difficult to interface with processor?
Static memory
ROM
Dynamic memory
RAM
348. Desirable characteristic(s) of a memory system is(are)
Speed and reliability
Durability and compactness
Low power consumption
All of these
349. The minimum time delay required between initiation of two successive memory operation is called
Memory cycle time
Transmission time
Memory access time
Skip time
350. Which of the following statement is wrong?
RAM is a type of volatile
Magnetic tape is non-volatile
Magnetic core and semiconductor memories are used as mass memory medium
An EPROM can be programmed, erased and reprogrammed by user with an EPROM programming instruction
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