2.6 Interrupt Operations
1. Interrupts
Interrupts are signals that alert the microprocessor to stop its current operations and attend to more urgent tasks.
An interrupt temporarily suspends the current process and allows the CPU to handle the interrupt, which is typically triggered by hardware devices or software.
Types of Interrupts:
Hardware Interrupts: Generated by external devices, such as input from a keyboard, mouse, or sensor.
Software Interrupts: Triggered by software instructions (e.g., a system call or software exception).
2. Interrupt Service Routines (ISRs)
Interrupt Service Routine (ISR) is a special function or set of instructions executed when a specific interrupt occurs.
Each interrupt is assigned an ISR, which is responsible for handling the interrupt and then returning control back to the main program.
Steps of ISR:
Interrupt Request (IRQ): An interrupt is raised by the hardware or software.
Interrupt Acknowledgment: The microprocessor acknowledges the interrupt.
Execution of ISR: The ISR is executed to handle the interrupt.
Return to Normal Operation: Once the interrupt is processed, the CPU resumes the previously interrupted task.
3. Interrupt Processing
The interrupt processing cycle involves the following steps:
Interrupt Occurrence: An interrupt is triggered.
Interrupt Detection: The processor detects the interrupt signal.
Interrupt Acknowledgment: The processor acknowledges the interrupt and saves the current execution state (e.g., registers, program counter) to preserve the ongoing task.
ISR Execution: The processor jumps to the corresponding ISR address to execute the interrupt-handling code.
Context Restoration: After the ISR is completed, the processor restores the saved execution state and resumes normal program execution.
4. Types of Interrupts:
Maskable Interrupts: Can be disabled (masked) by the CPU to avoid interruption during critical processes.
Non-Maskable Interrupts (NMI): Cannot be disabled and have higher priority, typically used for critical events like hardware failure.
5. Interrupt Priority
When multiple interrupts occur simultaneously, the processor must determine which one to address first. This is often done through an interrupt priority scheme.
Fixed Priority: Each interrupt source has a fixed priority level, and the processor serves the highest-priority interrupt.
Dynamic Priority: The priority may be changed depending on the circumstances or the type of interrupt.
6. Interrupt Vector Table
The interrupt vector table is a table in memory that stores the addresses of ISRs for various interrupt sources.
When an interrupt occurs, the processor looks up the ISR address in the interrupt vector table to know where to jump for processing.
Conclusion
Interrupts are signals that temporarily pause the CPU's tasks to handle urgent events, triggered by hardware (e.g., keyboard) or software (e.g., exceptions). An ISR manages each interrupt, ensuring tasks resume after processing. Interrupts can be maskable (disable-able) or non-maskable (critical, high-priority). The CPU uses an interrupt vector table to locate ISR addresses.
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