2.2 JFET and MOSFET

2.2 JFET and MOSFET

Introduction to Field-Effect Transistors

Field-Effect Transistors (FETs) represent a major class of semiconductor devices where the current flow is controlled by an electric field, as opposed to the current-controlled mechanism of Bipolar Junction Transistors (BJTs). This voltage-controlled operation offers key advantages: very high input impedance, lower power consumption, and simpler biasing. This section covers two primary types of FETs: the Junction FET (JFET) and the more dominant Metal-Oxide-Semiconductor FET (MOSFET), which forms the foundation of modern digital and analog integrated circuits.

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1. Junction Field-Effect Transistor (JFET)

1.1 Construction

1. Basic Structure:

   • A bar of semiconductor material (either N-type or P-type) forms the channel.

   • The ends of the bar are the Drain (D) and Source (S) terminals.

   • The sides of the channel are heavily doped with the opposite type of semiconductor to form PN junctions.

   • The two junctions are connected together internally to form the Gate (G) terminal.

2. Types:

   • N-Channel JFET: The channel is N-type semiconductor. The gate is made of P+ material.

   • P-Channel JFET: The channel is P-type semiconductor. The gate is made of N+ material.

   • The N-channel JFET is more common due to higher electron mobility.

1.2 Operation and Working Principle

1. Pinch-Off Voltage ($V_P$ or $V_{GS(off)}$):

   • The gate-to-source voltage ($V_{GS}$) that reduces the channel width to zero, effectively pinching off the drain current.

   • For an N-channel JFET, $V_{GS}$ must be negative (or zero) to control the channel.

2. Depletion Region Control:

   • The JFET operates with the gate-channel PN junction reverse-biased.

   • With $V_{GS} = 0$ and a small $V_{DS}$, a maximum current ($I_{DSS}$) flows.

   • As $V_{GS}$ becomes more negative, the depletion region of the reverse-biased PN junction widens, constricting the conductive channel.

   • This constriction increases channel resistance, thereby reducing the drain current ($I_D$).

   • At $V_{GS} = V_P$, the channel is fully depleted and $I_D \approx 0$.

1.3 Characteristics

1. Output Characteristics ($I_D$ vs. $V_{DS}$):

   • The plot shows a family of curves for different fixed $V_{GS}$ values.

   • Ohmic/Linear Region: At low $V_{DS}$, $I_D$ increases linearly with $V_{DS}$. The channel acts like a voltage-controlled resistor.

   • Saturation/Active Region: Beyond a certain $V_{DS}$ ($V_{DS} > V_{GS} - V_P$), $I_D$ becomes essentially constant and is controlled primarily by $V_{GS}$. This is the region used for amplification.

   • Breakdown Region: At very high $V_{DS}$, the drain-gate junction breaks down, causing a rapid increase in $I_D$.

2. Transfer Characteristic ($I_D$ vs. $V_{GS}$):

   • In the saturation region, the relationship is approximately parabolic (square law): $I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2$ where $I_{DSS}$ is the drain current with gate shorted to source ($V_{GS}=0$).

3. Key Parameters:

   • $I_{DSS}$: Saturation drain current at $V_{GS}=0$.

   • $V_P$ (or $V_{GS(off)}$): Pinch-off voltage.

   • Transconductance ($g_m$): Rate of change of $I_D$ with respect to $V_{GS}$, $g_m = \frac{\Delta I_D}{\Delta V_{GS}}$.

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2. Metal-Oxide-Semiconductor FET (MOSFET)

2.1 Structure and Operation

1. Basic Structure:

   • A substrate (body) of P-type or N-type semiconductor.

   • Two heavily doped regions of opposite type (N+ for PMOS, P+ for NMOS) diffused into the substrate, forming the Source (S) and Drain (D).

   • A thin layer of silicon dioxide ($SiO_2$) insulator is grown over the channel region between source and drain.

   • A Gate (G) electrode (metal or polysilicon) is deposited on top of this oxide layer, forming a capacitor.

2. Principle of Operation: Current flows through an inverted channel induced at the semiconductor surface under the gate oxide. The gate voltage controls the formation and conductivity of this channel through the field effect.

2.2 MOSFET Types: Enhancement and Depletion

2.2.1 Enhancement MOSFET (E-MOSFET)

1. Construction: No physical channel exists between source and drain at zero gate bias. The device is normally OFF.

2. Operation:

   • For an N-channel E-MOSFET, applying a positive gate-source voltage ($V_{GS} > 0$) attracts electrons (minority carriers in the P-substrate) to the surface under the gate.

   • This forms a thin N-type layer—an inversion channel—connecting the source and drain, allowing current to flow.

   • The minimum $V_{GS}$ required to create this channel is called the Threshold Voltage ($V_{TH}$ or $V_T$).

   • As $V_{GS}$ increases above $V_T$, the channel becomes more conductive, increasing $I_D$.

2.2.2 Depletion MOSFET (D-MOSFET)

1. Construction: A physical diffused channel exists between source and drain at the time of manufacturing. The device is normally ON at $V_{GS}=0$.

2. Operation:

   • For an N-channel D-MOSFET, the channel is N-type.

   • With $V_{GS} = 0$, a maximum drain current ($I_{DSS}$) flows.

   • Applying a negative $V_{GS}$ depletes the channel of charge carriers, reducing $I_D$ (depletion mode).

   • Applying a positive $V_{GS}$ enhances the channel, increasing $I_D$ beyond $I_{DSS}$ (enhancement mode).

   • This device can operate in both depletion and enhancement modes.

2.3 MOSFET I-V Characteristics

1. Output Characteristics ($I_D$ vs. $V_{DS}$):

   • Cut-off Region: $V_{GS} < V_T$. No channel, $I_D \approx 0$.

   • Triode/Linear Region: $V_{DS} < (V_{GS} - V_T)$. The channel is continuous and acts like a voltage-controlled resistor.

     • $I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_T)V_{DS} - \frac{V_{DS}^2}{2}\right]$

   • Saturation/Active Region: $V_{DS} \ge (V_{GS} - V_T)$. The channel "pinches off" near the drain. $I_D$ is largely independent of $V_{DS}$.

     • $I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2 (1 + \lambda V_{DS})$ where:

     • $\mu_n$: Carrier mobility.

     • $C_{ox}$: Gate oxide capacitance per unit area.

     • $W/L$: Aspect Ratio (Width-to-Length of the channel).

     • $\lambda$: Channel-length modulation parameter.

2. Transfer Characteristic ($I_D$ vs. $V_{GS}$):

   • In the saturation region, the square-law relationship is clearly visible.

3. Key Parameters:

   • $V_T$ (Threshold Voltage): Voltage at which the channel forms/enhances significantly.

   • $k_n$ or $\beta$ (Transconductance Parameter): $k_n = \mu_n C_{ox} \frac{W}{L}$.

   • $g_m$ (Transconductance): $g_m = \frac{\partial I_D}{\partial V_{GS}} = \sqrt{2 k_n I_D} = \frac{2I_D}{V_{GS}-V_T}$.

   • $r_o$ (Output Resistance): Due to channel-length modulation, $r_o = \frac{1}{\lambda I_D}$.

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3. MOSFET Applications

3.1 MOSFET as an Amplifier

1. Principle: Operate the MOSFET in its saturation region where it provides a high, linear voltage-controlled current source.

2. Common Configurations:

   • Common Source (CS): Provides high voltage and power gain. Most frequently used.

   • Common Gate (CG): Low input impedance, high output impedance, current buffer.

   • Common Drain (Source Follower): Voltage gain ≈ 1, high input impedance, low output impedance (voltage buffer).

3. Voltage Gain ($A_v$) for CS Amplifier: $A_v = -g_m (r_o || R_D) \approx -g_m R_D$ (if $r_o >> R_D$).

4. Advantages: Extremely high input impedance, no gate current, simpler biasing than BJTs.

3.2 MOSFET as a Switch (Digital Application)

1. Principle: Exploit the cut-off and triode regions of operation.

2. Operation:

   • OFF State (Logic '0'): $V_{GS} < V_T$. MOSFET is in cut-off, $I_D \approx 0$. High impedance between D and S. $V_{out} \approx V_{DD}$.

   • ON State (Logic '1'): $V_{GS} > V_T$ and $V_{DS}$ is kept small. MOSFET operates in the triode region, acting as a low resistance ($R_{DS(on)}$) switch. $V_{out} \approx 0$.

3. Key Metrics:

   • Switching Speed: Limited by the time required to charge/discharge parasitic capacitances ($C_{gs}, C_{gd}, C_{db}$).

   • Power Dissipation: $P_{dynamic} = C_L V_{DD}^2 f$ (switching power) + $I_{leakage} V_{DD}$ (static power).

3.3 MOSFET Biasing Techniques

The goal is to establish a stable DC operating point (Q-point) in the saturation region for amplification.

1. Fixed Bias: Simple but highly sensitive to variations in $V_T$ and $k_n$. Not practical.

2. Self (Source) Bias (for D-MOSFETs): Uses a source resistor $R_S$ to provide negative feedback, stabilizing $I_D$. Requires a bypass capacitor for AC gain.

3. Voltage Divider Bias: Most common and stable method for E-MOSFETs. Uses two resistors ($R_{G1}, R_{G2}$) from $V_{DD}$ to ground to set $V_G$. The source resistor $R_S$ sets $I_D$.

   • $V_G = V_{DD} \frac{R_{G2}}{R_{G1}+R_{G2}}$

   • $V_S = I_D R_S$

   • $V_{GS} = V_G - V_S$

4. Feedback Bias: Uses a resistor from drain to gate to provide DC feedback, stabilizing the Q-point.

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4. Complementary MOS (CMOS)

4.1 Working Principle

1. Definition: CMOS technology uses complementary pairs of P-channel and N-channel Enhancement MOSFETs on the same substrate.

2. Basic CMOS Inverter:

   • Structure: A PMOS (pull-up) and an NMOS (pull-down) transistor connected in series between $V_{DD}$ and GND. Their gates are connected together as the input, and their drains are connected together as the output.

   • Operation:

     • Input = LOW (0V): NMOS is OFF ($V_{GS} = 0 < V_{TN}$). PMOS is ON ($V_{GS} = -V_{DD} < V_{TP}$, negative for PMOS). Output is pulled HIGH to $V_{DD}$ through the PMOS.

     • Input = HIGH ($V_{DD}$): NMOS is ON. PMOS is OFF. Output is pulled LOW to GND through the NMOS.

3. Key Features:

   • Static Power Dissipation: Nearly Zero. In either steady logic state, one transistor is always OFF, preventing a DC path from $V_{DD}$ to GND.

   • Rail-to-Rail Output Swing: Output switches fully between GND and $V_{DD}$.

   • High Noise Margins.

   • Power Dissipation is primarily dynamic ($P = C_L V_{DD}^2 f$).

4.2 CMOS Fabrication and Logic Families

1. N-Well/P-Well Process: The standard process for creating both NMOS and PMOS transistors on a single chip.

2. Scaling (Moore's Law): Continuous reduction of transistor dimensions (channel length, oxide thickness) leading to higher speed, lower power per function, and higher density.

3. Logic Gates: All basic gates (NAND, NOR, etc.) are constructed using complementary pull-up (PMOS) and pull-down (NMOS) networks.

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5. Applications of MOSFET and CMOS

1. Digital Integrated Circuits (ICs):

   • Microprocessors & Microcontrollers: The CPU core.

   • Memory Chips: SRAM, DRAM, Flash memory.

   • Digital Signal Processors (DSPs).

   • Field-Programmable Gate Arrays (FPGAs).

2. Analog and Mixed-Signal ICs:

   • Operational Amplifiers (Op-amps): CMOS op-amps are standard.

   • Analog Switches and Multiplexers.

   • Data Converters: Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters.

   • Phase-Locked Loops (PLLs).

3. Power Electronics:

   • Power MOSFETs: Designed to handle high currents and voltages. Used as efficient switches in switch-mode power supplies (SMPS), motor drivers, and power amplifiers.

   • MOSFET as a Voltage-Controlled Resistor: In automatic gain control (AGC) circuits, electronic potentiometers.

4. Radio Frequency (RF) Circuits:

   • RF Amplifiers (LNAs, PAs): CMOS technology is dominant in RF transceivers for wireless communication.

5. Sensors and Actuators:

   • Integrated with sensing elements (e.g., CMOS Image Sensors in digital cameras).

   • Microelectromechanical Systems (MEMS) drivers.

Conclusion: The MOSFET, particularly in its complementary CMOS form, is the undisputed workhorse of modern electronics. Its voltage-controlled operation, scalability, and ability to integrate millions of devices on a single chip have enabled the digital revolution. From the fundamental amplifier and switch to the complex processor and memory cell, a deep understanding of JFET and MOSFET principles is essential for any electrical or electronics engineer.