3. Digital Logic and Microprocessor

3. Digital Logic and Microprocessor (AEEE03)

• 3.1 Digital Logic

  • Number systems (binary, decimal, hexadecimal)

  • Logic levels (HIGH/LOW, voltage ranges)

  • Basic logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR)

  • Boolean algebra laws and theorems

  • Standard forms: Sum-of-Products (SOP) and Product-of-Sums (POS)

  • Conversion from truth table to Karnaugh map for simplification

• 3.2 Combinational and Arithmetic Circuits

  • Combinational Logic Devices:

    • Multiplexers (MUX) and Demultiplexers (DEMUX)

    • Decoders and Encoders (priority encoders)

  • Arithmetic Circuits:

    • Binary addition and subtraction

    • Half Adders and Full Adders

    • Operations with unsigned and signed (two's complement) binary numbers

• 3.3 Sequential Logic Circuits

  • Flip-Flops: RS, gated (clocked), edge-triggered (D, JK), and master-slave

  • Registers: Types (parallel-in parallel-out, shift registers) and applications (data storage, serial-to-parallel conversion)

  • Counters: Asynchronous (ripple) counters and Synchronous counters

• 3.4 Microprocessor

  • Internal architecture (ALU, Registers, Control Unit, Bus)

  • Key features (word size, clock speed, instruction set)

  • Basics of assembly language programming (mnemonics, addressing, simple programs)

• 3.5 Interfacing (Microprocessor System)

  • Memory device classification and hierarchy (cache, RAM, ROM)

  • Basic concepts of interfacing I/O devices and memory

  • Parallel interface

  • Programmable Peripheral Interface (PPI - e.g., 8255)

  • Serial interface: synchronous vs. asynchronous communication

  • Serial communication standards: RS-232, RS-423, RS-422, Universal Serial Bus (USB)

  • Introduction to USART, Direct Memory Access (DMA), and DMA controllers

• 3.6 Computer Organization

  • Control Unit: Hardwired vs. microprogrammed control

  • Control memory and addressing sequencing

  • Microinstruction format

  • CPU Structure and Function: ALU, register file

  • Instruction formats and addressing modes (immediate, direct, indirect, indexed)

  • Data transfer and manipulation instructions

  • Processor architecture: RISC vs. CISC

  • Performance enhancement techniques: Pipelining and parallel processing concepts