The address symbol table is generated by the assembler during the assembly process. It maps symbolic addresses to their corresponding memory addresses.
452. When an instruction is read from the memory, it is called
Memory read cycle
Fetch cycle
Instruction cycle
Memory write cycle
Show me the answer
Answer: 2. Fetch cycle
Explanation:
The fetch cycle is the process of retrieving an instruction from memory. It is the first step in the instruction cycle.
453. Which activity does not take place during execution cycle?
ALU performs the arithmetic and logical operation
Effective address is calculated
Next instruction is fetched
Branch address is calculated and branching conditions are checked
Show me the answer
Answer: 3. Next instruction is fetched
Explanation:
The next instruction is fetched during the fetch cycle, not the execution cycle. The execution cycle involves performing operations like ALU calculations, effective address calculation, and branching.
454. The time for which the D-input of a D-FF must not change after the clock is applied is known as
Hold time
Set-up time
Transition time
Delay time
Show me the answer
Answer: 1. Hold time
Explanation:
Hold time is the minimum time for which the input (D-input) must remain stable after the clock edge to ensure proper operation of the flip-flop.
455. How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16?
64
16
32
128
Show me the answer
Answer: 1. 64
Explanation:
Each chip provides 128 x 8 bits = 1024 bits. For 4096 x 16 bits = 65536 bits, the number of chips required is 65536 / 1024 = 64.
456. In addition of two signed numbers, represented in 2's complement form generates an overflow if
A. B = 0
A = 0
A. B = 1
A + B = 1
Show me the answer
Answer: 3. A. B = 1
Explanation:
Overflow occurs in 2's complement addition if the sign bits of the operands are the same but differ from the sign bit of the result.
457. In DMA the data transfer is controlled by...
Microprocessor
RAM
Memory
I/O devices
Show me the answer
Answer: 4. I/O devices
Explanation:
In DMA (Direct Memory Access), data transfer is controlled by I/O devices, bypassing the CPU to directly access memory.
458. Synchronous means...
At irregular intervals
At same time
At variable time
None of the above
Show me the answer
Answer: 2. At same time
Explanation:
Synchronous operations occur at the same time or are coordinated by a clock signal.
459. Excess-3 equivalent representation of (1234) H is
(1237) Ex-3
(4567) Ex-3
(7993) Ex-3
(4663) Ex-3
Show me the answer
Answer: 2. (4567) Ex-3
Explanation:
Excess-3 code is obtained by adding 3 to each digit of the hexadecimal number. For (1234)H, the Excess-3 equivalent is (4567)Ex-3.
460. Which of the memory holds the information when the Power Supply is switched off?
Static RAM
Dynamic RAM
EEROM
None of the above
Show me the answer
Answer: 3. EEROM
Explanation:
EEROM (Electrically Erasable Read-Only Memory) retains data even when the power is switched off, unlike volatile memories like SRAM and DRAM.
461. Minimum no. of NAND gate required implementing an Ex-OR function is
2
3
4
5
Show me the answer
Answer: 3. 4
Explanation:
A minimum of 4 NAND gates are required to implement an XOR function.
462. Which of the following expression is not equivalent to x?
x NAND x
x NOR x
x NAND 1
x NOR 1
Show me the answer
Answer: 4. x NOR 1
Explanation:
The expression x NOR 1 is equivalent to NOT x, which is not the same as x.
463. BCD equivalent of Two's complement is
Nine's complement
One's complement+1
Ten's complement
None of the above
Show me the answer
Answer: 3. Ten's complement
Explanation:
The BCD equivalent of Two's complement is Ten's complement.
464. Associative memory is sometimes called as...
Virtual memory
Cache memory
Main memory
Content addressable memory
Show me the answer
Answer: 4. Content addressable memory
Explanation:
Associative memory is also known as Content Addressable Memory (CAM), where data is accessed based on its content rather than an address.
465. When CPU is not fully loaded, which of the following method of data transfer is preferred?
DMA
Interrupt
Polling
None of the above
Show me the answer
Answer: 2. Interrupt
Explanation:
When the CPU is not fully loaded, interrupt-driven data transfer is preferred as it allows the CPU to handle other tasks while waiting for I/O operations.
466. 8085 microprocessor carryout the subtraction by
BCD subtraction method
Hexadecimal subtraction method
2's complement method
Floating Point subtraction method
Show me the answer
Answer: 3. 2's complement method
Explanation:
The 8085 microprocessor performs subtraction using the 2's complement method.
467. PAL circuit consists of
Fixed OR & programmable AND logic
Programmable OR & Fixed AND Logic
Fixed OR & fixed AND logic
Programmable OR & programmable AND logic
Show me the answer
Answer: 1. Fixed OR & programmable AND logic
Explanation:
PAL (Programmable Array Logic) consists of a fixed OR array and a programmable AND array.
468. CPU checks for an interrupt signal during
Starting of last Machine cycle
First T-State of interrupt cycle
Last T-State of instruction cycle
Fetch cycle
Show me the answer
Answer: 3. Last T-State of instruction cycle
Explanation:
The CPU checks for interrupt signals during the last T-State of the instruction cycle.
469. Which of the following is not a characteristic of RISC architecture......?
Larger instruction set
Simple addressing mode
One instruction per cycle
Register to register operation
Show me the answer
Answer: 1. Larger instruction set
Explanation:
RISC architecture is characterized by a smaller instruction set, not a larger one.
470. Memory interleaving technique is used to address the memory modules in order to have
Higher average utilization
Faster access to a block of data
Reduced complexity in mapping hardware
Both (A) and (B)
Show me the answer
Answer: 4. Both (A) and (B)
Explanation:
Memory interleaving improves average utilization and provides faster access to data blocks by distributing memory accesses across multiple modules.
471. In a multiprogramming system, which of the following is used?
Data parallelism
L1 cache
Paging concept
None of the above
Show me the answer
Answer: 3. Paging concept
Explanation:
Multiprogramming systems use the paging concept to manage memory efficiently and allow multiple programs to run concurrently.
472. Cycle stealing technique is used in
Interrupt based data transfer
DMA based data transfer
Polled mode data transfer
None of the above
Show me the answer
Answer: 2. DMA based data transfer
Explanation:
Cycle stealing is a technique used in DMA (Direct Memory Access) where the DMA controller temporarily takes control of the bus to transfer data.
473. During DMA acknowledge cycle, CPU relinquishes
Address bus only
Control bus and data bus
Address bus and control bus
Data bus and address bus
Show me the answer
Answer: 4. Data bus and address bus
Explanation:
During a DMA acknowledge cycle, the CPU relinquishes control of the data bus and address bus to the DMA controller.
474. If the stack pointer is initialized with (4FEB) H, then after execution of Push operation in 8085 microprocessors, the Stack Pointer shall be
4FEA
4FEC
4FED
4FE9
Show me the answer
Answer: 1. 4FEA
Explanation:
In the 8085 microprocessor, the stack pointer decrements by 2 after a push operation. So, 4FEB - 2 = 4FEA.
475. A more efficient way to organize a Page Table is by means of an associative memory having
Number of words equal to number of pages
Number of words more than the number of pages
Number of words less than the number of pages
Any one of the above
Show me the answer
Answer: 1. Number of words equal to number of pages
Explanation:
An associative memory (like a TLB) is most efficient when the number of words equals the number of pages.
476. If there are four ROM ICs of 8K and two RAM ICs of 4K words, then the address range of 1st RAM is (Assume initial addresses correspond to ROMs)
(8000) H to (9FFF) H
(8000) H to (8FFF) H
(6000) H to (7FFF) H
(9000) H to (9FFF) H
Show me the answer
Answer: 2. (8000) H to (8FFF) H
Explanation:
The first RAM starts after the ROMs. Since ROMs occupy 32K (4 x 8K), the RAM starts at 8000H and ends at 8FFFH.
477. A.B.C is equal to A B C for
A=0, B=1, C=0
A=1, B=0, C=1
A=1, B=1, C=1
All of the above
Show me the answer
Answer: 4. All of the above
Explanation:
The expression A.B.C is equivalent to A B C for all combinations of A, B, and C.
478. Gray code equivalent of (1000)2 is
1111
1100
1000
None of the above
Show me the answer
Answer: 2. 1100
Explanation:
The Gray code equivalent of binary 1000 is 1100.
479. The memory blocks are mapped on to the cache with the help of......
Hash functions
Vectors
Mapping functions
None of the above
Show me the answer
Answer: 3. Mapping functions
Explanation:
Memory blocks are mapped to cache using mapping functions like direct, associative, or set-associative mapping.
480. During a write operation if the required block is not present in the cache then...... occurs
Write latency
Write hit
Write delay
Write miss
Show me the answer
Answer: 4. Write miss
Explanation:
A write miss occurs when the required block is not present in the cache during a write operation.
481. In...... protocol the information is directly written into main....
Write through
Write back
Write first
None of the above
Show me the answer
Answer: 1. Write through
Explanation:
In the write-through protocol, data is written directly to both the cache and the main memory.
482. The method of mapping the consecutive memory blocks to consecutive cache blocks is called....
Set associative
Associative
Direct
Indirect
Show me the answer
Answer: 3. Direct
Explanation:
Direct mapping maps consecutive memory blocks to consecutive cache blocks in a fixed manner.
483. While using the direct mapping technique, in a 16-bit system the higher order 5 bits is used for....
Tag
Block
Word
Id
Show me the answer
Answer: 1. Tag
Explanation:
In direct mapping, the higher-order bits are used as the tag to identify the memory block.
484. The technique of searching for a block by going through all tags is......
Linear search
Binary search
Associative search
None of the above
Show me the answer
Answer: 3. Associative search
Explanation:
Associative search involves comparing all tags simultaneously to find a match.
485. In case of Zero-address instruction method the operands are stored in....
Register
Accumulators
Push down stack
Cache
Show me the answer
Answer: 3. Push down stack
Explanation:
In zero-address instructions, operands are stored in a push-down stack.
486. The addressing mode which makes use of in-direction pointer is......
Indirect addressing mode
Index addressing mode
Relative addressing mode
Offset addressing mode
Show me the answer
Answer: 1. Indirect addressing mode
Explanation:
Indirect addressing mode uses a pointer to the memory location where the actual operand is stored.
487. The addressing mode, where you directly specify the operand value is
Immediate
Direct
Definite
Relative
Show me the answer
Answer: 1. Immediate
Explanation:
Immediate addressing mode directly specifies the operand value in the instruction.
488. ...addressing mode is most suitable to change the normal sequence of execution of instructions.
Relative
Indirect
Index with offset
Immediate
Show me the answer
Answer: 1. Relative
Explanation:
Relative addressing mode is used to change the normal sequence of execution by specifying an offset from the current instruction pointer.
489. The pipelining process is also called as....
Superscalar operation
Assembly line operation
Von Neumann cycle
None of the mentioned
Show me the answer
Answer: 2. Assembly line operation
Explanation:
Pipelining is often compared to an assembly line, where multiple stages of instruction execution overlap.
490. The fetch and execution cycles are interleaved with the help of......
Modification in processor architecture
Clock
Special unit
Control unit
Show me the answer
Answer: 2. Clock
Explanation:
The clock synchronizes the fetch and execution cycles, allowing them to interleave efficiently.
491. The situation where in the data of operands are not available is called...
Data hazard
Stock
Deadlock
Structural hazard
Show me the answer
Answer: 1. Data hazard
Explanation:
A data hazard occurs when the data required for an instruction is not yet available.
492. The reason for the implementation of the cache memory is
To increase the internal memory of the system
The difference in speeds of operation of the processor and memory
To reduce the memory access and cycle time
All of the above
Show me the answer
Answer: 2. The difference in speeds of operation of the processor and memory
Explanation:
Cache memory is implemented to bridge the speed gap between the processor and main memory.
493. The effectiveness of the cache memory is based on the property of ______.
Locality of reference
Memory localization
Memory size
None of the above
Show me the answer
Answer: 1. Locality of reference
Explanation:
Cache memory leverages the principle of locality of reference, where programs tend to access the same data or nearby data repeatedly.
494. The temporal aspect of the locality of reference means
That the recently executed instruction won't be executed soon
That the recently executed instruction is temporarily not referenced
That the recently executed instruction will be executed soon again
None of the above
Show me the answer
Answer: 3. That the recently executed instruction will be executed soon again
Explanation:
Temporal locality refers to the tendency of a program to reuse the same data or instructions in the near future.
495. The spatial aspect of the locality of reference means
That the recently executed instruction is executed again next
That the recently executed won't be executed again
That the instruction executed will be executed at a later time
That the instruction in close proximity of the instruction executed will be executed in future
Show me the answer
Answer: 4. That the instruction in close proximity of the instruction executed will be executed in future
Explanation:
Spatial locality refers to the tendency of a program to access data or instructions that are close to recently accessed data.
496. The algorithm to remove and place new contents into the cache is called ______.
Renewal algorithm
Updating
Replacement algorithm
None of the above
Show me the answer
Answer: 3. Replacement algorithm
Explanation:
The replacement algorithm determines which cache block to replace when new data needs to be loaded.
497. The key factor/s in commercial success of a computer is/are......
Performance
Cost
Speed
Both A and B
Show me the answer
Answer: 4. Both A and B
Explanation:
The commercial success of a computer depends on both performance and cost.
498. The main objective of the computer system is
To provide optimal power operation
To provide best performance at low cost
To provide speedy operation at low power consumption
All of the above
Show me the answer
Answer: 2. To provide best performance at low cost
Explanation:
The primary objective of a computer system is to deliver the best performance at the lowest possible cost.
499. A common measure of performance is:
Price/performance ratio
Performance /price ratio
Operation/price ratio
None of the above
Show me the answer
Answer: 1. Price/performance ratio
Explanation:
The price/performance ratio is a common metric used to evaluate the efficiency of a computer system.
500. The main purpose of having memory hierarchy is to
Reduce access time
Provide large capacity
Reduce propagation time
Both A and B
Show me the answer
Answer: 4. Both A and B
Explanation:
Memory hierarchy aims to reduce access time and provide large storage capacity.
