8087
80287
80387
80486DX
Answer: 4. 80486DX
Explanation:
The 80486DX microprocessor has an internal coprocessor for floating-point arithmetic. This integration eliminates the need for a separate coprocessor chip, improving performance and reducing cost.
Control unit and numeric control unit
Integer unit and control unit
Floating point unit and coprocessor unit
Coprocessor unit and numeric control unit
Answer: 1. Control unit and numeric control unit
Explanation:
A coprocessor typically consists of two major sections:
Control unit: Manages the overall operation of the coprocessor.
Numeric control unit: Handles the execution of numeric and floating-point operations.
SPARC
80386
MC68030
MC68020
Answer: 1. SPARC
Explanation:
SPARC (Scalable Processor Architecture) is a RISC-based processor architecture developed by Sun Microsystems. It is designed for high performance and scalability, making it suitable for workstations and servers.
80% instruction is generated and 20% instruction is executed
80% instruction is executed and 20% instruction is generated
80% instruction is executed and 20% instruction is not executed
80% instruction is generated and 20% instructions are not generated
Answer: 2. 80% instruction is executed and 20% instruction is generated
Explanation:
The 80/20 rule in computer architecture states that 80% of the execution time is spent on 20% of the instructions. This observation is used to optimize performance by focusing on the most frequently executed instructions.
SPARC
MC68030
MC68030
8086
Answer: 1. SPARC
Explanation:
SPARC architecture is more complex compared to the 8086 and MC68030. It is a RISC-based architecture designed for high performance and scalability, with advanced features like pipelining and superscalar execution.
Intel
IBM
Motorola
MIPS
Answer: 2. IBM
Explanation:
IBM was one of the first companies to define and develop RISC (Reduced Instruction Set Computer) architecture. Their work laid the foundation for modern RISC processors.
8086
8088
8087
MIPS R2000
Answer: 4. MIPS R2000
Explanation:
The MIPS R2000 is a RISC processor that executes most instructions in a single clock cycle. This is a key feature of RISC architectures, which aim to simplify instruction execution for higher performance.
Load and store instruction
Opcode instruction
Memory instruction
Bus instruction
Answer: 1. Load and store instruction
Explanation:
In RISC architecture, memory is accessed using load and store instructions. These instructions move data between memory and registers, while all other operations are performed on registers.
EDSAC
SSEM
PIC
CSIRAC
Answer: 3. PIC
Explanation:
The PIC microcontroller uses Harvard architecture, which separates the memory for instructions and data. This allows simultaneous access to both, improving performance.
Shared bus between the program memory and data memory
Separate bus between the program memory and data memory
External bus for program memory and data memory
External bus for data memory only
Answer: 1. Shared bus between the program memory and data memory
Explanation:
Von Neumann architecture uses a shared bus for both program memory and data memory. This simplifies the design but can create a bottleneck, as instructions and data cannot be accessed simultaneously.
Content-addressable memory
Complex addressable memory
Computing addressable memory
Concurrently addressable memory
Answer: 1. Content-addressable memory
Explanation:
CAM (Content-Addressable Memory) is a type of memory that allows data to be accessed based on its content rather than its address. It is used in applications like cache memory and network routers.
TEXAS TMS320
80386
80286
8086
Answer: 1. TEXAS TMS320
Explanation:
The TEXAS TMS320 series of digital signal processors (DSPs) uses Harvard architecture, which separates instruction and data memory for improved performance in signal processing tasks.
Intel
Motorola
University of Berkeley
MIPS
Answer: 3. University of Berkeley
Explanation:
The University of Berkeley played a significant role in further developing RISC architecture. Their research led to the creation of the RISC-I and RISC-II processors, which influenced modern RISC designs.
Von Neumann architecture
Harvard
RISC
CISC
Answer: 1. Von Neumann architecture
Explanation:
Princeton architecture is another name for Von Neumann architecture, which uses a shared bus for both instructions and data. It is named after the Princeton Institute for Advanced Study, where it was developed.
David Patterson
Von Neumann
Michael J Flynn
Harvard
Answer: 1. David Patterson
Explanation:
David Patterson, a computer scientist at the University of California, Berkeley, coined the term RISC (Reduced Instruction Set Computer) in the early 1980s. His work laid the foundation for modern RISC architectures.
AVR
Zilog80
8051
Motorola 6800
Answer: 1. AVR
Explanation:
The AVR microcontroller is an 8-bit RISC processor with Harvard architecture. It is widely used in embedded systems due to its simplicity and efficiency.
AVR
Atmel
Blackfin
Zilog Z80
Answer: 4. Zilog Z80
Explanation:
The Zilog Z80 is a CISC (Complex Instruction Set Computer) processor. It has a large instruction set and is known for its use in early personal computers and embedded systems.
Flash memory
PROM
EPROM
ROM
Answer: 4. ROM
Explanation:
ROM (Read-Only Memory) is the most basic form of non-volatile memory. It retains data even when power is off and is used to store firmware and bootloaders.
Dr. Fujio Masuoka
John Ellis
Josh Fisher
John Ruttenberg
Answer: 1. Dr. Fujio Masuoka
Explanation:
Dr. Fujio Masuoka, a Japanese engineer, invented flash memory while working at Toshiba in the 1980s. Flash memory is widely used in USB drives, SSDs, and memory cards.
RAM
Flash memory
Shifters
ROM
